# NB: The timing numbers in this architecture file have been modified # to comply with our NDA with the foundry providing us with process # information. The critical path delay output by VPR WILL NOT be accurate, # as we have intentionally altered the delays to introduce inaccuracy. # The numbers are still reasonable enough to allow CAD experimentation, # though. If you want real timing numbers, you'll have to insert your own # process data for the various, R, C, and Tdel entries. # This architecture referred to Xilinx virtex 2 # Architecture with two types of routing segment. The routing is # fully-populated. One length of segment is buffered, the other uses pass # transistors. # Uniform channels. Each pin appears on only one side. io_rat 10 #4 pads per row or column #chan_width_io 1 chan_width_io 1 #chan_width_x uniform 1 chan_width_x uniform 1 #chan_width_y uniform 1 chan_width_y uniform 1 #Cluster of size 2, with 33 input 14 output inpin class: 0 bottom #SLICE_SOPIN inpin class: 0 left #SLICE_ALTDIG inpin class: 0 top #SLICE_CE inpin class: 2 global right #SLICE_CLK inpin class: 0 bottom #SLICE_SR outpin class: 1 left #SLICE_DIG outpin class: 1 top #SLICE_SOPOUT inpin class: 0 right #SLICE_CIN outpin class: 1 bottom #SLICE_COUT #Subblock 0 inpin class: 0 bottom #B_SHIFTIN outpin class: 1 left #B_SHIFTOUT inpin class: 0 left #B_BY outpin class: 1 top #B_BYOUT outpin class: 1 right #B_YB outpin class: 1 bottom #B_Y inpin class: 0 left #B_DY outpin class: 1 top #B_YQ inpin class: 0 left #B_FXINA inpin class: 0 left #B_FXINB outpin class: 1 right #B_FX inpin class: 0 top #B_LUT0 inpin class: 0 right #B_LUT1 inpin class: 0 bottom #B_LUT2 inpin class: 0 left #B_LUT3 #Subblock 1 inpin class: 0 bottom #B_SHIFTIN outpin class: 1 left #B_SHIFTOUT inpin class: 0 left #B_BY outpin class: 1 top #B_BYOUT outpin class: 1 right #B_YB outpin class: 1 bottom #B_Y inpin class: 0 left #B_DY outpin class: 1 top #B_YQ inpin class: 0 left #B_FXINA inpin class: 0 left #B_FXINB outpin class: 1 right #B_FX inpin class: 0 top #B_LUT0 inpin class: 0 right #B_LUT1 inpin class: 0 bottom #B_LUT2 inpin class: 0 left #B_LUT3 #Class 0 is LUT inputs, class 1 is the output, class 2 is the clock. subblocks_per_clb 2 subblock_lut_size 4 subblock_num_pin 20 subblock_num_ipin 13 subblock_num_opin 7 dsp rep: 30 start: 1 dsp_outpin class: 0 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 1 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 2 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 3 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 4 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 5 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 6 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 7 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 8 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 9 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 10 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 11 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 12 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 13 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 14 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 15 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 16 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 17 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 18 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 19 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 20 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 21 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 22 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 23 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 24 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 25 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 26 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 27 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 28 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 29 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 30 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 31 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 32 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 33 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 34 cap: 1.0e-15 right #P (0-35) dsp_outpin class: 35 cap: 1.0e-15 right #P (0-35) dsp_inpin class: 36 cap: 1.0e-15 left #A(0 -17) dsp_inpin class: 37 cap: 1.0e-15 left #A(0 -17) dsp_inpin class: 38 cap: 1.0e-15 left #A(0 -17) dsp_inpin class: 39 cap: 1.0e-15 left #A(0 -17) dsp_inpin class: 40 cap: 1.0e-15 left #A(0 -17) dsp_inpin class: 41 cap: 1.0e-15 left #A(0 -17) dsp_inpin class: 42 cap: 1.0e-15 left #A(0 -17) dsp_inpin class: 43 cap: 1.0e-15 left #A(0 -17) dsp_inpin class: 44 cap: 1.0e-15 left #A(0 -17) dsp_inpin class: 45 cap: 1.0e-15 left #A(0 -17) dsp_inpin class: 46 cap: 1.0e-15 left #A(0 -17) dsp_inpin class: 47 cap: 1.0e-15 left #A(0 -17) dsp_inpin class: 48 cap: 1.0e-15 left #A(0 -17) dsp_inpin class: 49 cap: 1.0e-15 left #A(0 -17) dsp_inpin class: 50 cap: 1.0e-15 left #A(0 -17) dsp_inpin class: 51 cap: 1.0e-15 left #A(0 -17) dsp_inpin class: 52 cap: 1.0e-15 left #A(0 -17) dsp_inpin class: 53 cap: 1.0e-15 left #A(0 -17) dsp_inpin class: 54 cap: 1.0e-15 left #B(0 -17) dsp_inpin class: 55 cap: 1.0e-15 left #B(0 -17) dsp_inpin class: 56 cap: 1.0e-15 left #B(0 -17) dsp_inpin class: 57 cap: 1.0e-15 left #B(0 -17) dsp_inpin class: 58 cap: 1.0e-15 left #B(0 -17) dsp_inpin class: 59 cap: 1.0e-15 left #B(0 -17) dsp_inpin class: 60 cap: 1.0e-15 left #B(0 -17) dsp_inpin class: 61 cap: 1.0e-15 left #B(0 -17) dsp_inpin class: 62 cap: 1.0e-15 left #B(0 -17) dsp_inpin class: 63 cap: 1.0e-15 left #B(0 -17) dsp_inpin class: 64 cap: 1.0e-15 left #B(0 -17) dsp_inpin class: 65 cap: 1.0e-15 left #B(0 -17) dsp_inpin class: 66 cap: 1.0e-15 left #B(0 -17) dsp_inpin class: 67 cap: 1.0e-15 left #B(0 -17) dsp_inpin class: 68 cap: 1.0e-15 left #B(0 -17) dsp_inpin class: 69 cap: 1.0e-15 left #B(0 -17) dsp_inpin class: 70 cap: 1.0e-15 left #B(0 -17) dsp_inpin class: 71 cap: 1.0e-15 left #B(0 -17) dsp_inpin class: 72 cap: 1.0e-15 global top #C dsp_inpin class: 73 cap: 1.0e-15 top #CE dsp_inpin class: 74 cap: 1.0e-15 top #R memory rep: 0 start: 0 memory_inpin class: 0 cap: 2.0e-15 type: we bottom memory_inpin class: 1 cap: 2.0e-15 type: address left memory_inpin class: 2 cap: 2.0e-15 type: address left memory_outpin class: 3 cap: 2.0e-15 type: data right memory_outpin class: 4 cap: 2.0e-15 type: data right memory_inpin class: 5 cap: 2.0e-15 type: clock global top memory_inpin class: 6 cap: 2.0e-15 type: clock global top #parameters needed only for detailed routing. switch_block_type subset #switch_block_type wilton Fc_type fractional Fc_output 1 Fc_input 1 Fc_pad 1 #Fc_type absolute #Fc_output 5 #Fc_input 5 #Fc_pad 5 # Metal 3, min W (0.28 um), min space (0.28um) segment frequency: 1 length: 1 wire_switch: 2 opin_switch: 2 Frac_cb: 1 \ Frac_sb: 1 Rmetal: 30.360 Cmetal: 3.046e-14 switch 0 buffered: yes R: 580.000 Cin: 3.500e-15 Cout: 1.500e-15 Tdel: 0 Leakage_Current: 7.9202e-9 # switch_1 width is approximatley 10.0 times minimum width switch 1 buffered: yes R: 580.000 Cin: 3.5200e-15 Cout: 1.50e-15 Tdel: 0 Leakage_Current: 2.3383e-8 # switch_2 width is approximatley 5.0 times minimum width switch 2 buffered: yes R: 580.000 Cin: 3.500e-15 Cout: 1.50e-15 Tdel: 0 Leakage_Current: 9e-9 #0.13 um width R_minW_nmos 900 R_minW_pmos 1710 # 1.9x R of an nmos # Timing info below. C_ipin_cblock 0.00000162e-9 #T_ipin_cblock 3.7700e-10 T_ipin_cblock 0.0085e-9 #T_ipad 1.555e-9 #Clk_to_Q + 2:1 mux T_ipad 0.69e-9 #Clk_to_Q + 2:1 mux #T_opad 1.455e-9 #T_opad 0.84e-9 T_opad 0.84e-11 T_clk_opad 0.0051e-9 #T_sblk_opin_to_sblk_ipin 3.0100e-10 T_sblk_opin_to_sblk_ipin 0 #T_clb_ipin_to_sblk_ipin 3.0100e-10 T_clb_ipin_to_sblk_ipin 0 T_sblk_opin_to_clb_opin 0 #T_sblk_cout_to_sblk_cin 3.01e-10 #T_clb_cout_to_clb_cin 3.01e-10 T_sblk_cout_to_sblk_cin 0.084e-9 T_clb_cout_to_clb_cin 2.105e-9 T_FX 0.01e-9 #virtex2 input to output = 6.49ns #clock to output = 4.11ns T_dsp T_internal: 2.37e-9 T_in: 0.01e-9 T_out: 4.11e-9 #T_dsp T_internal: 0.4e-9 T_in: 0.3e-9 T_out: 0.2e-9 T_memory T_internal: 4e-10 T_in: 3e-10 T_out: 2e-10 #T_subblock T_comb: 0.35e-9 T_seq_in: 0.032e-9 T_seq_out: 11e-12 T_subblock T_comb: 0.347e-9 T_seq_in: 0.293e-9 T_seq_out: 0.45e-9 T_subblock T_comb: 0.347e-9 T_seq_in: 0.293e-9 T_seq_out: 0.45e-9 #T_subblock T_comb: 0.35e-9 T_seq_in: 0.032e-9 T_seq_out: 11e-12 #T_subblock T_comb: 4e-10 T_seq_in: 3e-10 T_seq_out: 2e-10 #T_subblock T_comb: 4e-10 T_seq_in: 3e-10 T_seq_out: 2e-10 global_clock_num 1 clock_network buffer_R: 129 buffer_Cin: 1.027e-14 buffer_Cout: 1.3905e-14 Rwire: 31.4824 Cwire: 3.3524e-15 Cin_per_clb_clock_pin: 1.62e-16 CLB_Cwire 2.5404e-14 temp -40 NMOS_NFS: 8.49e18 PMOS_NFS: 8.50e18 temp -30 NMOS_NFS: 8.71e18 PMOS_NFS: 8.65e18 temp -20 NMOS_NFS: 8.93e18 PMOS_NFS: 8.80e18 temp -10 NMOS_NFS: 8.15e18 PMOS_NFS: 8.97e18 temp 0 NMOS_NFS: 9.37e18 PMOS_NFS: 8.14e18 temp 10 NMOS_NFS: 9.59e18 PMOS_NFS: 8.32e18 temp 20 NMOS_NFS: 9.81e18 PMOS_NFS: 9.49e18 temp 25 NMOS_NFS: 9.92e18 PMOS_NFS: 9.58e18 temp 30 NMOS_NFS: 1.00e18 PMOS_NFS: 9.67e18 temp 40 NMOS_NFS: 1.03e19 PMOS_NFS: 9.85e18 temp 50 NMOS_NFS: 1.05e19 PMOS_NFS: 1.00e18 temp 60 NMOS_NFS: 1.07e19 PMOS_NFS: 1.02e18 temp 70 NMOS_NFS: 1.09e19 PMOS_NFS: 1.04e19 temp 80 NMOS_NFS: 1.11e19 PMOS_NFS: 1.06e19 temp 90 NMOS_NFS: 1.13e19 PMOS_NFS: 1.07e19 temp 100 NMOS_NFS: 1.15e19 PMOS_NFS: 1.09e19 Nmos Vth: 0.42 CJ: 1.0143E-3 CJSW: 1.672E-10 CJSWG: 4.130E-10 CGDO: 3.4E-10 COX: 8.46e-3 EC: 4.17e6 Pmos Vth: 0.5 CJ: 1.2412E-3 CJSW: 2.765E-10 CJSWG: 4.570E-10 CGDO: 3.725E-10 COX: 8.46e-3 EC: 5.28e6 poly Cpoly: 1.43E-10 poly_extention: 0.22e-6 min_transistor_size length: 0.18e-6 width: 0.22e-6 Vdd 1.8 Vswing 1.8 Vgs_for_leakage 0.2 SRAM_leakage 0 short_circuit_power_percentage 0.1 P_dsp C_cycle: 3.0e-14 P_leak: 1e-6 P_memory C_readcycle: 3.0e-14 C_writecycle: 2.0e-14 P_leak: 1e-6