-- -- Written by Synplicity -- Product Version "Version 9.0.1" -- Program "Synplify Pro", Mapper "9.0.0, Build 156R" -- Tue Jun 17 01:10:57 2008 -- -- -- Written by Synplify Pro version 9.0.0, Build 156R -- Tue Jun 17 01:10:57 2008 -- -- No definition of black box work.fpmult.syn_black_box -- No definition of black box work.fpadder.syn_black_box -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library synplify; use synplify.components.all; library UNISIM; use UNISIM.VCOMPONENTS.all; entity dscg is port( rst : in std_logic; we : in std_logic; clk : in std_logic; one : in std_logic_vector(31 downto 0); cos : in std_logic_vector(31 downto 0); s1 : in std_logic_vector(31 downto 0); s2 : in std_logic_vector(31 downto 0); a_config : in std_logic_vector(3 downto 0); m_config : in std_logic_vector(3 downto 0); s1out : out std_logic_vector(31 downto 0); s2out : out std_logic_vector(31 downto 0); a_status : out std_logic_vector(27 downto 0); m_status : out std_logic_vector(27 downto 0)); end dscg; architecture beh of dscg is signal A_CONFIG_REG : std_logic_vector(3 downto 0); signal COS_REG : std_logic_vector(31 downto 0); signal ONE_REG : std_logic_vector(31 downto 0); signal ADD1 : std_logic_vector(31 downto 0); signal A_STATUS_2 : std_logic_vector(6 downto 0); signal X2 : std_logic_vector(31 downto 0); signal X3 : std_logic_vector(31 downto 0); signal ADD4 : std_logic_vector(31 downto 0); signal A_STATUS_1 : std_logic_vector(27 downto 7); signal SUB5 : std_logic_vector(31 downto 0); signal X6 : std_logic_vector(31 downto 0); signal X7 : std_logic_vector(31 downto 0); signal ADD8 : std_logic_vector(31 downto 0); signal M_CONFIG_REG : std_logic_vector(3 downto 0); signal S2_REG : std_logic_vector(31 downto 0); signal M_STATUS_2 : std_logic_vector(6 downto 0); signal S1_REG : std_logic_vector(31 downto 0); signal X3_1 : std_logic_vector(31 downto 0); signal M_STATUS_1 : std_logic_vector(27 downto 7); signal X7_1 : std_logic_vector(31 downto 0); signal X7_REG1 : std_logic_vector(31 downto 0); signal X7_REG2 : std_logic_vector(31 downto 0); signal X7_REG3 : std_logic_vector(31 downto 0); signal X7_REG4 : std_logic_vector(31 downto 0); signal X7_REG5 : std_logic_vector(31 downto 0); signal X3_REG1 : std_logic_vector(31 downto 0); signal X3_REG2 : std_logic_vector(31 downto 0); signal X3_REG3 : std_logic_vector(31 downto 0); signal X3_REG4 : std_logic_vector(31 downto 0); signal X3_REG5 : std_logic_vector(31 downto 0); signal ONE_C : std_logic_vector(31 downto 0); signal COS_C : std_logic_vector(31 downto 0); signal S1_C : std_logic_vector(31 downto 0); signal S2_C : std_logic_vector(31 downto 0); signal A_CONFIG_C : std_logic_vector(3 downto 0); signal M_CONFIG_C : std_logic_vector(3 downto 0); signal S1OUT_C : std_logic_vector(31 downto 0); signal S2OUT_C : std_logic_vector(31 downto 0); signal WE_REG : std_logic ; signal WE_C : std_logic ; signal CLK_C : std_logic ; signal NN_1 : std_logic ; signal NN_2 : std_logic ; component fpadder port( clk : in std_logic; we : in std_logic; config : in std_logic; FA : in std_logic_vector(31 downto 0); FB : in std_logic_vector(31 downto 0); Q : out std_logic_vector(31 downto 0); status : out std_logic_vector(6 downto 0) ); end component; component fpmult port( clk : in std_logic; we : in std_logic; config : in std_logic; FA : in std_logic_vector(31 downto 0); FB : in std_logic_vector(31 downto 0); Q : out std_logic_vector(31 downto 0); status : out std_logic_vector(6 downto 0) ); end component; begin U_A1: fpadder port map ( clk => CLK_C, we => WE_REG, config => A_CONFIG_REG(0), FA(0) => COS_REG(0), FA(1) => COS_REG(1), FA(2) => COS_REG(2), FA(3) => COS_REG(3), FA(4) => COS_REG(4), FA(5) => COS_REG(5), FA(6) => COS_REG(6), FA(7) => COS_REG(7), FA(8) => COS_REG(8), FA(9) => COS_REG(9), FA(10) => COS_REG(10), FA(11) => COS_REG(11), FA(12) => COS_REG(12), FA(13) => COS_REG(13), FA(14) => COS_REG(14), FA(15) => COS_REG(15), FA(16) => COS_REG(16), FA(17) => COS_REG(17), FA(18) => COS_REG(18), FA(19) => COS_REG(19), FA(20) => COS_REG(20), FA(21) => COS_REG(21), FA(22) => COS_REG(22), FA(23) => COS_REG(23), FA(24) => COS_REG(24), FA(25) => COS_REG(25), FA(26) => COS_REG(26), FA(27) => COS_REG(27), FA(28) => COS_REG(28), FA(29) => COS_REG(29), FA(30) => COS_REG(30), FA(31) => COS_REG(31), FB(0) => ONE_REG(0), FB(1) => ONE_REG(1), FB(2) => ONE_REG(2), FB(3) => ONE_REG(3), FB(4) => ONE_REG(4), FB(5) => ONE_REG(5), FB(6) => ONE_REG(6), FB(7) => ONE_REG(7), FB(8) => ONE_REG(8), FB(9) => ONE_REG(9), FB(10) => ONE_REG(10), FB(11) => ONE_REG(11), FB(12) => ONE_REG(12), FB(13) => ONE_REG(13), FB(14) => ONE_REG(14), FB(15) => ONE_REG(15), FB(16) => ONE_REG(16), FB(17) => ONE_REG(17), FB(18) => ONE_REG(18), FB(19) => ONE_REG(19), FB(20) => ONE_REG(20), FB(21) => ONE_REG(21), FB(22) => ONE_REG(22), FB(23) => ONE_REG(23), FB(24) => ONE_REG(24), FB(25) => ONE_REG(25), FB(26) => ONE_REG(26), FB(27) => ONE_REG(27), FB(28) => ONE_REG(28), FB(29) => ONE_REG(29), FB(30) => ONE_REG(30), FB(31) => ONE_REG(31), Q(0) => ADD1(0), Q(1) => ADD1(1), Q(2) => ADD1(2), Q(3) => ADD1(3), Q(4) => ADD1(4), Q(5) => ADD1(5), Q(6) => ADD1(6), Q(7) => ADD1(7), Q(8) => ADD1(8), Q(9) => ADD1(9), Q(10) => ADD1(10), Q(11) => ADD1(11), Q(12) => ADD1(12), Q(13) => ADD1(13), Q(14) => ADD1(14), Q(15) => ADD1(15), Q(16) => ADD1(16), Q(17) => ADD1(17), Q(18) => ADD1(18), Q(19) => ADD1(19), Q(20) => ADD1(20), Q(21) => ADD1(21), Q(22) => ADD1(22), Q(23) => ADD1(23), Q(24) => ADD1(24), Q(25) => ADD1(25), Q(26) => ADD1(26), Q(27) => ADD1(27), Q(28) => ADD1(28), Q(29) => ADD1(29), Q(30) => ADD1(30), Q(31) => ADD1(31), status(0) => A_STATUS_2(0), status(1) => A_STATUS_2(1), status(2) => A_STATUS_2(2), status(3) => A_STATUS_2(3), status(4) => A_STATUS_2(4), status(5) => A_STATUS_2(5), status(6) => A_STATUS_2(6)); U_A2: fpadder port map ( clk => CLK_C, we => WE_REG, config => A_CONFIG_REG(1), FA(0) => X2(0), FA(1) => X2(1), FA(2) => X2(2), FA(3) => X2(3), FA(4) => X2(4), FA(5) => X2(5), FA(6) => X2(6), FA(7) => X2(7), FA(8) => X2(8), FA(9) => X2(9), FA(10) => X2(10), FA(11) => X2(11), FA(12) => X2(12), FA(13) => X2(13), FA(14) => X2(14), FA(15) => X2(15), FA(16) => X2(16), FA(17) => X2(17), FA(18) => X2(18), FA(19) => X2(19), FA(20) => X2(20), FA(21) => X2(21), FA(22) => X2(22), FA(23) => X2(23), FA(24) => X2(24), FA(25) => X2(25), FA(26) => X2(26), FA(27) => X2(27), FA(28) => X2(28), FA(29) => X2(29), FA(30) => X2(30), FA(31) => X2(31), FB(0) => X3(0), FB(1) => X3(1), FB(2) => X3(2), FB(3) => X3(3), FB(4) => X3(4), FB(5) => X3(5), FB(6) => X3(6), FB(7) => X3(7), FB(8) => X3(8), FB(9) => X3(9), FB(10) => X3(10), FB(11) => X3(11), FB(12) => X3(12), FB(13) => X3(13), FB(14) => X3(14), FB(15) => X3(15), FB(16) => X3(16), FB(17) => X3(17), FB(18) => X3(18), FB(19) => X3(19), FB(20) => X3(20), FB(21) => X3(21), FB(22) => X3(22), FB(23) => X3(23), FB(24) => X3(24), FB(25) => X3(25), FB(26) => X3(26), FB(27) => X3(27), FB(28) => X3(28), FB(29) => X3(29), FB(30) => X3(30), FB(31) => X3(31), Q(0) => ADD4(0), Q(1) => ADD4(1), Q(2) => ADD4(2), Q(3) => ADD4(3), Q(4) => ADD4(4), Q(5) => ADD4(5), Q(6) => ADD4(6), Q(7) => ADD4(7), Q(8) => ADD4(8), Q(9) => ADD4(9), Q(10) => ADD4(10), Q(11) => ADD4(11), Q(12) => ADD4(12), Q(13) => ADD4(13), Q(14) => ADD4(14), Q(15) => ADD4(15), Q(16) => ADD4(16), Q(17) => ADD4(17), Q(18) => ADD4(18), Q(19) => ADD4(19), Q(20) => ADD4(20), Q(21) => ADD4(21), Q(22) => ADD4(22), Q(23) => ADD4(23), Q(24) => ADD4(24), Q(25) => ADD4(25), Q(26) => ADD4(26), Q(27) => ADD4(27), Q(28) => ADD4(28), Q(29) => ADD4(29), Q(30) => ADD4(30), Q(31) => ADD4(31), status(0) => A_STATUS_1(7), status(1) => A_STATUS_1(8), status(2) => A_STATUS_1(9), status(3) => A_STATUS_1(10), status(4) => A_STATUS_1(11), status(5) => A_STATUS_1(12), status(6) => A_STATUS_1(13)); U_A3: fpadder port map ( clk => CLK_C, we => WE_REG, config => A_CONFIG_REG(2), FA(0) => ONE_REG(0), FA(1) => ONE_REG(1), FA(2) => ONE_REG(2), FA(3) => ONE_REG(3), FA(4) => ONE_REG(4), FA(5) => ONE_REG(5), FA(6) => ONE_REG(6), FA(7) => ONE_REG(7), FA(8) => ONE_REG(8), FA(9) => ONE_REG(9), FA(10) => ONE_REG(10), FA(11) => ONE_REG(11), FA(12) => ONE_REG(12), FA(13) => ONE_REG(13), FA(14) => ONE_REG(14), FA(15) => ONE_REG(15), FA(16) => ONE_REG(16), FA(17) => ONE_REG(17), FA(18) => ONE_REG(18), FA(19) => ONE_REG(19), FA(20) => ONE_REG(20), FA(21) => ONE_REG(21), FA(22) => ONE_REG(22), FA(23) => ONE_REG(23), FA(24) => ONE_REG(24), FA(25) => ONE_REG(25), FA(26) => ONE_REG(26), FA(27) => ONE_REG(27), FA(28) => ONE_REG(28), FA(29) => ONE_REG(29), FA(30) => ONE_REG(30), FA(31) => ONE_REG(31), FB(0) => COS_REG(0), FB(1) => COS_REG(1), FB(2) => COS_REG(2), FB(3) => COS_REG(3), FB(4) => COS_REG(4), FB(5) => COS_REG(5), FB(6) => COS_REG(6), FB(7) => COS_REG(7), FB(8) => COS_REG(8), FB(9) => COS_REG(9), FB(10) => COS_REG(10), FB(11) => COS_REG(11), FB(12) => COS_REG(12), FB(13) => COS_REG(13), FB(14) => COS_REG(14), FB(15) => COS_REG(15), FB(16) => COS_REG(16), FB(17) => COS_REG(17), FB(18) => COS_REG(18), FB(19) => COS_REG(19), FB(20) => COS_REG(20), FB(21) => COS_REG(21), FB(22) => COS_REG(22), FB(23) => COS_REG(23), FB(24) => COS_REG(24), FB(25) => COS_REG(25), FB(26) => COS_REG(26), FB(27) => COS_REG(27), FB(28) => COS_REG(28), FB(29) => COS_REG(29), FB(30) => COS_REG(30), FB(31) => COS_REG(31), Q(0) => SUB5(0), Q(1) => SUB5(1), Q(2) => SUB5(2), Q(3) => SUB5(3), Q(4) => SUB5(4), Q(5) => SUB5(5), Q(6) => SUB5(6), Q(7) => SUB5(7), Q(8) => SUB5(8), Q(9) => SUB5(9), Q(10) => SUB5(10), Q(11) => SUB5(11), Q(12) => SUB5(12), Q(13) => SUB5(13), Q(14) => SUB5(14), Q(15) => SUB5(15), Q(16) => SUB5(16), Q(17) => SUB5(17), Q(18) => SUB5(18), Q(19) => SUB5(19), Q(20) => SUB5(20), Q(21) => SUB5(21), Q(22) => SUB5(22), Q(23) => SUB5(23), Q(24) => SUB5(24), Q(25) => SUB5(25), Q(26) => SUB5(26), Q(27) => SUB5(27), Q(28) => SUB5(28), Q(29) => SUB5(29), Q(30) => SUB5(30), Q(31) => SUB5(31), status(0) => A_STATUS_1(14), status(1) => A_STATUS_1(15), status(2) => A_STATUS_1(16), status(3) => A_STATUS_1(17), status(4) => A_STATUS_1(18), status(5) => A_STATUS_1(19), status(6) => A_STATUS_1(20)); U_A4: fpadder port map ( clk => CLK_C, we => WE_REG, config => A_CONFIG_REG(3), FA(0) => X6(0), FA(1) => X6(1), FA(2) => X6(2), FA(3) => X6(3), FA(4) => X6(4), FA(5) => X6(5), FA(6) => X6(6), FA(7) => X6(7), FA(8) => X6(8), FA(9) => X6(9), FA(10) => X6(10), FA(11) => X6(11), FA(12) => X6(12), FA(13) => X6(13), FA(14) => X6(14), FA(15) => X6(15), FA(16) => X6(16), FA(17) => X6(17), FA(18) => X6(18), FA(19) => X6(19), FA(20) => X6(20), FA(21) => X6(21), FA(22) => X6(22), FA(23) => X6(23), FA(24) => X6(24), FA(25) => X6(25), FA(26) => X6(26), FA(27) => X6(27), FA(28) => X6(28), FA(29) => X6(29), FA(30) => X6(30), FA(31) => X6(31), FB(0) => X7(0), FB(1) => X7(1), FB(2) => X7(2), FB(3) => X7(3), FB(4) => X7(4), FB(5) => X7(5), FB(6) => X7(6), FB(7) => X7(7), FB(8) => X7(8), FB(9) => X7(9), FB(10) => X7(10), FB(11) => X7(11), FB(12) => X7(12), FB(13) => X7(13), FB(14) => X7(14), FB(15) => X7(15), FB(16) => X7(16), FB(17) => X7(17), FB(18) => X7(18), FB(19) => X7(19), FB(20) => X7(20), FB(21) => X7(21), FB(22) => X7(22), FB(23) => X7(23), FB(24) => X7(24), FB(25) => X7(25), FB(26) => X7(26), FB(27) => X7(27), FB(28) => X7(28), FB(29) => X7(29), FB(30) => X7(30), FB(31) => X7(31), Q(0) => ADD8(0), Q(1) => ADD8(1), Q(2) => ADD8(2), Q(3) => ADD8(3), Q(4) => ADD8(4), Q(5) => ADD8(5), Q(6) => ADD8(6), Q(7) => ADD8(7), Q(8) => ADD8(8), Q(9) => ADD8(9), Q(10) => ADD8(10), Q(11) => ADD8(11), Q(12) => ADD8(12), Q(13) => ADD8(13), Q(14) => ADD8(14), Q(15) => ADD8(15), Q(16) => ADD8(16), Q(17) => ADD8(17), Q(18) => ADD8(18), Q(19) => ADD8(19), Q(20) => ADD8(20), Q(21) => ADD8(21), Q(22) => ADD8(22), Q(23) => ADD8(23), Q(24) => ADD8(24), Q(25) => ADD8(25), Q(26) => ADD8(26), Q(27) => ADD8(27), Q(28) => ADD8(28), Q(29) => ADD8(29), Q(30) => ADD8(30), Q(31) => ADD8(31), status(0) => A_STATUS_1(21), status(1) => A_STATUS_1(22), status(2) => A_STATUS_1(23), status(3) => A_STATUS_1(24), status(4) => A_STATUS_1(25), status(5) => A_STATUS_1(26), status(6) => A_STATUS_1(27)); U_X1: fpmult port map ( clk => CLK_C, we => WE_REG, config => M_CONFIG_REG(0), FA(0) => ADD1(0), FA(1) => ADD1(1), FA(2) => ADD1(2), FA(3) => ADD1(3), FA(4) => ADD1(4), FA(5) => ADD1(5), FA(6) => ADD1(6), FA(7) => ADD1(7), FA(8) => ADD1(8), FA(9) => ADD1(9), FA(10) => ADD1(10), FA(11) => ADD1(11), FA(12) => ADD1(12), FA(13) => ADD1(13), FA(14) => ADD1(14), FA(15) => ADD1(15), FA(16) => ADD1(16), FA(17) => ADD1(17), FA(18) => ADD1(18), FA(19) => ADD1(19), FA(20) => ADD1(20), FA(21) => ADD1(21), FA(22) => ADD1(22), FA(23) => ADD1(23), FA(24) => ADD1(24), FA(25) => ADD1(25), FA(26) => ADD1(26), FA(27) => ADD1(27), FA(28) => ADD1(28), FA(29) => ADD1(29), FA(30) => ADD1(30), FA(31) => ADD1(31), FB(0) => S2_REG(0), FB(1) => S2_REG(1), FB(2) => S2_REG(2), FB(3) => S2_REG(3), FB(4) => S2_REG(4), FB(5) => S2_REG(5), FB(6) => S2_REG(6), FB(7) => S2_REG(7), FB(8) => S2_REG(8), FB(9) => S2_REG(9), FB(10) => S2_REG(10), FB(11) => S2_REG(11), FB(12) => S2_REG(12), FB(13) => S2_REG(13), FB(14) => S2_REG(14), FB(15) => S2_REG(15), FB(16) => S2_REG(16), FB(17) => S2_REG(17), FB(18) => S2_REG(18), FB(19) => S2_REG(19), FB(20) => S2_REG(20), FB(21) => S2_REG(21), FB(22) => S2_REG(22), FB(23) => S2_REG(23), FB(24) => S2_REG(24), FB(25) => S2_REG(25), FB(26) => S2_REG(26), FB(27) => S2_REG(27), FB(28) => S2_REG(28), FB(29) => S2_REG(29), FB(30) => S2_REG(30), FB(31) => S2_REG(31), Q(0) => X2(0), Q(1) => X2(1), Q(2) => X2(2), Q(3) => X2(3), Q(4) => X2(4), Q(5) => X2(5), Q(6) => X2(6), Q(7) => X2(7), Q(8) => X2(8), Q(9) => X2(9), Q(10) => X2(10), Q(11) => X2(11), Q(12) => X2(12), Q(13) => X2(13), Q(14) => X2(14), Q(15) => X2(15), Q(16) => X2(16), Q(17) => X2(17), Q(18) => X2(18), Q(19) => X2(19), Q(20) => X2(20), Q(21) => X2(21), Q(22) => X2(22), Q(23) => X2(23), Q(24) => X2(24), Q(25) => X2(25), Q(26) => X2(26), Q(27) => X2(27), Q(28) => X2(28), Q(29) => X2(29), Q(30) => X2(30), Q(31) => X2(31), status(0) => M_STATUS_2(0), status(1) => M_STATUS_2(1), status(2) => M_STATUS_2(2), status(3) => M_STATUS_2(3), status(4) => M_STATUS_2(4), status(5) => M_STATUS_2(5), status(6) => M_STATUS_2(6)); U_X2: fpmult port map ( clk => CLK_C, we => WE_REG, config => M_CONFIG_REG(1), FA(0) => COS_REG(0), FA(1) => COS_REG(1), FA(2) => COS_REG(2), FA(3) => COS_REG(3), FA(4) => COS_REG(4), FA(5) => COS_REG(5), FA(6) => COS_REG(6), FA(7) => COS_REG(7), FA(8) => COS_REG(8), FA(9) => COS_REG(9), FA(10) => COS_REG(10), FA(11) => COS_REG(11), FA(12) => COS_REG(12), FA(13) => COS_REG(13), FA(14) => COS_REG(14), FA(15) => COS_REG(15), FA(16) => COS_REG(16), FA(17) => COS_REG(17), FA(18) => COS_REG(18), FA(19) => COS_REG(19), FA(20) => COS_REG(20), FA(21) => COS_REG(21), FA(22) => COS_REG(22), FA(23) => COS_REG(23), FA(24) => COS_REG(24), FA(25) => COS_REG(25), FA(26) => COS_REG(26), FA(27) => COS_REG(27), FA(28) => COS_REG(28), FA(29) => COS_REG(29), FA(30) => COS_REG(30), FA(31) => COS_REG(31), FB(0) => S1_REG(0), FB(1) => S1_REG(1), FB(2) => S1_REG(2), FB(3) => S1_REG(3), FB(4) => S1_REG(4), FB(5) => S1_REG(5), FB(6) => S1_REG(6), FB(7) => S1_REG(7), FB(8) => S1_REG(8), FB(9) => S1_REG(9), FB(10) => S1_REG(10), FB(11) => S1_REG(11), FB(12) => S1_REG(12), FB(13) => S1_REG(13), FB(14) => S1_REG(14), FB(15) => S1_REG(15), FB(16) => S1_REG(16), FB(17) => S1_REG(17), FB(18) => S1_REG(18), FB(19) => S1_REG(19), FB(20) => S1_REG(20), FB(21) => S1_REG(21), FB(22) => S1_REG(22), FB(23) => S1_REG(23), FB(24) => S1_REG(24), FB(25) => S1_REG(25), FB(26) => S1_REG(26), FB(27) => S1_REG(27), FB(28) => S1_REG(28), FB(29) => S1_REG(29), FB(30) => S1_REG(30), FB(31) => S1_REG(31), Q(0) => X3_1(0), Q(1) => X3_1(1), Q(2) => X3_1(2), Q(3) => X3_1(3), Q(4) => X3_1(4), Q(5) => X3_1(5), Q(6) => X3_1(6), Q(7) => X3_1(7), Q(8) => X3_1(8), Q(9) => X3_1(9), Q(10) => X3_1(10), Q(11) => X3_1(11), Q(12) => X3_1(12), Q(13) => X3_1(13), Q(14) => X3_1(14), Q(15) => X3_1(15), Q(16) => X3_1(16), Q(17) => X3_1(17), Q(18) => X3_1(18), Q(19) => X3_1(19), Q(20) => X3_1(20), Q(21) => X3_1(21), Q(22) => X3_1(22), Q(23) => X3_1(23), Q(24) => X3_1(24), Q(25) => X3_1(25), Q(26) => X3_1(26), Q(27) => X3_1(27), Q(28) => X3_1(28), Q(29) => X3_1(29), Q(30) => X3_1(30), Q(31) => X3_1(31), status(0) => M_STATUS_1(7), status(1) => M_STATUS_1(8), status(2) => M_STATUS_1(9), status(3) => M_STATUS_1(10), status(4) => M_STATUS_1(11), status(5) => M_STATUS_1(12), status(6) => M_STATUS_1(13)); U_X3: fpmult port map ( clk => CLK_C, we => WE_REG, config => M_CONFIG_REG(2), FA(0) => SUB5(0), FA(1) => SUB5(1), FA(2) => SUB5(2), FA(3) => SUB5(3), FA(4) => SUB5(4), FA(5) => SUB5(5), FA(6) => SUB5(6), FA(7) => SUB5(7), FA(8) => SUB5(8), FA(9) => SUB5(9), FA(10) => SUB5(10), FA(11) => SUB5(11), FA(12) => SUB5(12), FA(13) => SUB5(13), FA(14) => SUB5(14), FA(15) => SUB5(15), FA(16) => SUB5(16), FA(17) => SUB5(17), FA(18) => SUB5(18), FA(19) => SUB5(19), FA(20) => SUB5(20), FA(21) => SUB5(21), FA(22) => SUB5(22), FA(23) => SUB5(23), FA(24) => SUB5(24), FA(25) => SUB5(25), FA(26) => SUB5(26), FA(27) => SUB5(27), FA(28) => SUB5(28), FA(29) => SUB5(29), FA(30) => SUB5(30), FA(31) => SUB5(31), FB(0) => S1_REG(0), FB(1) => S1_REG(1), FB(2) => S1_REG(2), FB(3) => S1_REG(3), FB(4) => S1_REG(4), FB(5) => S1_REG(5), FB(6) => S1_REG(6), FB(7) => S1_REG(7), FB(8) => S1_REG(8), FB(9) => S1_REG(9), FB(10) => S1_REG(10), FB(11) => S1_REG(11), FB(12) => S1_REG(12), FB(13) => S1_REG(13), FB(14) => S1_REG(14), FB(15) => S1_REG(15), FB(16) => S1_REG(16), FB(17) => S1_REG(17), FB(18) => S1_REG(18), FB(19) => S1_REG(19), FB(20) => S1_REG(20), FB(21) => S1_REG(21), FB(22) => S1_REG(22), FB(23) => S1_REG(23), FB(24) => S1_REG(24), FB(25) => S1_REG(25), FB(26) => S1_REG(26), FB(27) => S1_REG(27), FB(28) => S1_REG(28), FB(29) => S1_REG(29), FB(30) => S1_REG(30), FB(31) => S1_REG(31), Q(0) => X6(0), Q(1) => X6(1), Q(2) => X6(2), Q(3) => X6(3), Q(4) => X6(4), Q(5) => X6(5), Q(6) => X6(6), Q(7) => X6(7), Q(8) => X6(8), Q(9) => X6(9), Q(10) => X6(10), Q(11) => X6(11), Q(12) => X6(12), Q(13) => X6(13), Q(14) => X6(14), Q(15) => X6(15), Q(16) => X6(16), Q(17) => X6(17), Q(18) => X6(18), Q(19) => X6(19), Q(20) => X6(20), Q(21) => X6(21), Q(22) => X6(22), Q(23) => X6(23), Q(24) => X6(24), Q(25) => X6(25), Q(26) => X6(26), Q(27) => X6(27), Q(28) => X6(28), Q(29) => X6(29), Q(30) => X6(30), Q(31) => X6(31), status(0) => M_STATUS_1(14), status(1) => M_STATUS_1(15), status(2) => M_STATUS_1(16), status(3) => M_STATUS_1(17), status(4) => M_STATUS_1(18), status(5) => M_STATUS_1(19), status(6) => M_STATUS_1(20)); U_X4: fpmult port map ( clk => CLK_C, we => WE_REG, config => M_CONFIG_REG(3), FA(0) => COS_REG(0), FA(1) => COS_REG(1), FA(2) => COS_REG(2), FA(3) => COS_REG(3), FA(4) => COS_REG(4), FA(5) => COS_REG(5), FA(6) => COS_REG(6), FA(7) => COS_REG(7), FA(8) => COS_REG(8), FA(9) => COS_REG(9), FA(10) => COS_REG(10), FA(11) => COS_REG(11), FA(12) => COS_REG(12), FA(13) => COS_REG(13), FA(14) => COS_REG(14), FA(15) => COS_REG(15), FA(16) => COS_REG(16), FA(17) => COS_REG(17), FA(18) => COS_REG(18), FA(19) => COS_REG(19), FA(20) => COS_REG(20), FA(21) => COS_REG(21), FA(22) => COS_REG(22), FA(23) => COS_REG(23), FA(24) => COS_REG(24), FA(25) => COS_REG(25), FA(26) => COS_REG(26), FA(27) => COS_REG(27), FA(28) => COS_REG(28), FA(29) => COS_REG(29), FA(30) => COS_REG(30), FA(31) => COS_REG(31), FB(0) => S2_REG(0), FB(1) => S2_REG(1), FB(2) => S2_REG(2), FB(3) => S2_REG(3), FB(4) => S2_REG(4), FB(5) => S2_REG(5), FB(6) => S2_REG(6), FB(7) => S2_REG(7), FB(8) => S2_REG(8), FB(9) => S2_REG(9), FB(10) => S2_REG(10), FB(11) => S2_REG(11), FB(12) => S2_REG(12), FB(13) => S2_REG(13), FB(14) => S2_REG(14), FB(15) => S2_REG(15), FB(16) => S2_REG(16), FB(17) => S2_REG(17), FB(18) => S2_REG(18), FB(19) => S2_REG(19), FB(20) => S2_REG(20), FB(21) => S2_REG(21), FB(22) => S2_REG(22), FB(23) => S2_REG(23), FB(24) => S2_REG(24), FB(25) => S2_REG(25), FB(26) => S2_REG(26), FB(27) => S2_REG(27), FB(28) => S2_REG(28), FB(29) => S2_REG(29), FB(30) => S2_REG(30), FB(31) => S2_REG(31), Q(0) => X7_1(0), Q(1) => X7_1(1), Q(2) => X7_1(2), Q(3) => X7_1(3), Q(4) => X7_1(4), Q(5) => X7_1(5), Q(6) => X7_1(6), Q(7) => X7_1(7), Q(8) => X7_1(8), Q(9) => X7_1(9), Q(10) => X7_1(10), Q(11) => X7_1(11), Q(12) => X7_1(12), Q(13) => X7_1(13), Q(14) => X7_1(14), Q(15) => X7_1(15), Q(16) => X7_1(16), Q(17) => X7_1(17), Q(18) => X7_1(18), Q(19) => X7_1(19), Q(20) => X7_1(20), Q(21) => X7_1(21), Q(22) => X7_1(22), Q(23) => X7_1(23), Q(24) => X7_1(24), Q(25) => X7_1(25), Q(26) => X7_1(26), Q(27) => X7_1(27), Q(28) => X7_1(28), Q(29) => X7_1(29), Q(30) => X7_1(30), Q(31) => X7_1(31), status(0) => M_STATUS_1(21), status(1) => M_STATUS_1(22), status(2) => M_STATUS_1(23), status(3) => M_STATUS_1(24), status(4) => M_STATUS_1(25), status(5) => M_STATUS_1(26), status(6) => M_STATUS_1(27)); WE_IBUF: IBUF port map ( O => WE_C, I => we); \ONE_IBUF[0]\: IBUF port map ( O => ONE_C(0), I => one(0)); \ONE_IBUF[1]\: IBUF port map ( O => ONE_C(1), I => one(1)); \ONE_IBUF[2]\: IBUF port map ( O => ONE_C(2), I => one(2)); \ONE_IBUF[3]\: IBUF port map ( O => ONE_C(3), I => one(3)); \ONE_IBUF[4]\: IBUF port map ( O => ONE_C(4), I => one(4)); \ONE_IBUF[5]\: IBUF port map ( O => ONE_C(5), I => one(5)); \ONE_IBUF[6]\: IBUF port map ( O => ONE_C(6), I => one(6)); \ONE_IBUF[7]\: IBUF port map ( O => ONE_C(7), I => one(7)); \ONE_IBUF[8]\: IBUF port map ( O => ONE_C(8), I => one(8)); \ONE_IBUF[9]\: IBUF port map ( O => ONE_C(9), I => one(9)); \ONE_IBUF[10]\: IBUF port map ( O => ONE_C(10), I => one(10)); \ONE_IBUF[11]\: IBUF port map ( O => ONE_C(11), I => one(11)); \ONE_IBUF[12]\: IBUF port map ( O => ONE_C(12), I => one(12)); \ONE_IBUF[13]\: IBUF port map ( O => ONE_C(13), I => one(13)); \ONE_IBUF[14]\: IBUF port map ( O => ONE_C(14), I => one(14)); \ONE_IBUF[15]\: IBUF port map ( O => ONE_C(15), I => one(15)); \ONE_IBUF[16]\: IBUF port map ( O => ONE_C(16), I => one(16)); \ONE_IBUF[17]\: IBUF port map ( O => ONE_C(17), I => one(17)); \ONE_IBUF[18]\: IBUF port map ( O => ONE_C(18), I => one(18)); \ONE_IBUF[19]\: IBUF port map ( O => ONE_C(19), I => one(19)); \ONE_IBUF[20]\: IBUF port map ( O => ONE_C(20), I => one(20)); \ONE_IBUF[21]\: IBUF port map ( O => ONE_C(21), I => one(21)); \ONE_IBUF[22]\: IBUF port map ( O => ONE_C(22), I => one(22)); \ONE_IBUF[23]\: IBUF port map ( O => ONE_C(23), I => one(23)); \ONE_IBUF[24]\: IBUF port map ( O => ONE_C(24), I => one(24)); \ONE_IBUF[25]\: IBUF port map ( O => ONE_C(25), I => one(25)); \ONE_IBUF[26]\: IBUF port map ( O => ONE_C(26), I => one(26)); \ONE_IBUF[27]\: IBUF port map ( O => ONE_C(27), I => one(27)); \ONE_IBUF[28]\: IBUF port map ( O => ONE_C(28), I => one(28)); \ONE_IBUF[29]\: IBUF port map ( O => ONE_C(29), I => one(29)); \ONE_IBUF[30]\: IBUF port map ( O => ONE_C(30), I => one(30)); \ONE_IBUF[31]\: IBUF port map ( O => ONE_C(31), I => one(31)); \COS_IBUF[0]\: IBUF port map ( O => COS_C(0), I => cos(0)); \COS_IBUF[1]\: IBUF port map ( O => COS_C(1), I => cos(1)); \COS_IBUF[2]\: IBUF port map ( O => COS_C(2), I => cos(2)); \COS_IBUF[3]\: IBUF port map ( O => COS_C(3), I => cos(3)); \COS_IBUF[4]\: IBUF port map ( O => COS_C(4), I => cos(4)); \COS_IBUF[5]\: IBUF port map ( O => COS_C(5), I => cos(5)); \COS_IBUF[6]\: IBUF port map ( O => COS_C(6), I => cos(6)); \COS_IBUF[7]\: IBUF port map ( O => COS_C(7), I => cos(7)); \COS_IBUF[8]\: IBUF port map ( O => COS_C(8), I => cos(8)); \COS_IBUF[9]\: IBUF port map ( O => COS_C(9), I => cos(9)); \COS_IBUF[10]\: IBUF port map ( O => COS_C(10), I => cos(10)); \COS_IBUF[11]\: IBUF port map ( O => COS_C(11), I => cos(11)); \COS_IBUF[12]\: IBUF port map ( O => COS_C(12), I => cos(12)); \COS_IBUF[13]\: IBUF port map ( O => COS_C(13), I => cos(13)); \COS_IBUF[14]\: IBUF port map ( O => COS_C(14), I => cos(14)); \COS_IBUF[15]\: IBUF port map ( O => COS_C(15), I => cos(15)); \COS_IBUF[16]\: IBUF port map ( O => COS_C(16), I => cos(16)); \COS_IBUF[17]\: IBUF port map ( O => COS_C(17), I => cos(17)); \COS_IBUF[18]\: IBUF port map ( O => COS_C(18), I => cos(18)); \COS_IBUF[19]\: IBUF port map ( O => COS_C(19), I => cos(19)); \COS_IBUF[20]\: IBUF port map ( O => COS_C(20), I => cos(20)); \COS_IBUF[21]\: IBUF port map ( O => COS_C(21), I => cos(21)); \COS_IBUF[22]\: IBUF port map ( O => COS_C(22), I => cos(22)); \COS_IBUF[23]\: IBUF port map ( O => COS_C(23), I => cos(23)); \COS_IBUF[24]\: IBUF port map ( O => COS_C(24), I => cos(24)); \COS_IBUF[25]\: IBUF port map ( O => COS_C(25), I => cos(25)); \COS_IBUF[26]\: IBUF port map ( O => COS_C(26), I => cos(26)); \COS_IBUF[27]\: IBUF port map ( O => COS_C(27), I => cos(27)); \COS_IBUF[28]\: IBUF port map ( O => COS_C(28), I => cos(28)); \COS_IBUF[29]\: IBUF port map ( O => COS_C(29), I => cos(29)); \COS_IBUF[30]\: IBUF port map ( O => COS_C(30), I => cos(30)); \COS_IBUF[31]\: IBUF port map ( O => COS_C(31), I => cos(31)); \S1_IBUF[0]\: IBUF port map ( O => S1_C(0), I => s1(0)); \S1_IBUF[1]\: IBUF port map ( O => S1_C(1), I => s1(1)); \S1_IBUF[2]\: IBUF port map ( O => S1_C(2), I => s1(2)); \S1_IBUF[3]\: IBUF port map ( O => S1_C(3), I => s1(3)); \S1_IBUF[4]\: IBUF port map ( O => S1_C(4), I => s1(4)); \S1_IBUF[5]\: IBUF port map ( O => S1_C(5), I => s1(5)); \S1_IBUF[6]\: IBUF port map ( O => S1_C(6), I => s1(6)); \S1_IBUF[7]\: IBUF port map ( O => S1_C(7), I => s1(7)); \S1_IBUF[8]\: IBUF port map ( O => S1_C(8), I => s1(8)); \S1_IBUF[9]\: IBUF port map ( O => S1_C(9), I => s1(9)); \S1_IBUF[10]\: IBUF port map ( O => S1_C(10), I => s1(10)); \S1_IBUF[11]\: IBUF port map ( O => S1_C(11), I => s1(11)); \S1_IBUF[12]\: IBUF port map ( O => S1_C(12), I => s1(12)); \S1_IBUF[13]\: IBUF port map ( O => S1_C(13), I => s1(13)); \S1_IBUF[14]\: IBUF port map ( O => S1_C(14), I => s1(14)); \S1_IBUF[15]\: IBUF port map ( O => S1_C(15), I => s1(15)); \S1_IBUF[16]\: IBUF port map ( O => S1_C(16), I => s1(16)); \S1_IBUF[17]\: IBUF port map ( O => S1_C(17), I => s1(17)); \S1_IBUF[18]\: IBUF port map ( O => S1_C(18), I => s1(18)); \S1_IBUF[19]\: IBUF port map ( O => S1_C(19), I => s1(19)); \S1_IBUF[20]\: IBUF port map ( O => S1_C(20), I => s1(20)); \S1_IBUF[21]\: IBUF port map ( O => S1_C(21), I => s1(21)); \S1_IBUF[22]\: IBUF port map ( O => S1_C(22), I => s1(22)); \S1_IBUF[23]\: IBUF port map ( O => S1_C(23), I => s1(23)); \S1_IBUF[24]\: IBUF port map ( O => S1_C(24), I => s1(24)); \S1_IBUF[25]\: IBUF port map ( O => S1_C(25), I => s1(25)); \S1_IBUF[26]\: IBUF port map ( O => S1_C(26), I => s1(26)); \S1_IBUF[27]\: IBUF port map ( O => S1_C(27), I => s1(27)); \S1_IBUF[28]\: IBUF port map ( O => S1_C(28), I => s1(28)); \S1_IBUF[29]\: IBUF port map ( O => S1_C(29), I => s1(29)); \S1_IBUF[30]\: IBUF port map ( O => S1_C(30), I => s1(30)); \S1_IBUF[31]\: IBUF port map ( O => S1_C(31), I => s1(31)); \S2_IBUF[0]\: IBUF port map ( O => S2_C(0), I => s2(0)); \S2_IBUF[1]\: IBUF port map ( O => S2_C(1), I => s2(1)); \S2_IBUF[2]\: IBUF port map ( O => S2_C(2), I => s2(2)); \S2_IBUF[3]\: IBUF port map ( O => S2_C(3), I => s2(3)); \S2_IBUF[4]\: IBUF port map ( O => S2_C(4), I => s2(4)); \S2_IBUF[5]\: IBUF port map ( O => S2_C(5), I => s2(5)); \S2_IBUF[6]\: IBUF port map ( O => S2_C(6), I => s2(6)); \S2_IBUF[7]\: IBUF port map ( O => S2_C(7), I => s2(7)); \S2_IBUF[8]\: IBUF port map ( O => S2_C(8), I => s2(8)); \S2_IBUF[9]\: IBUF port map ( O => S2_C(9), I => s2(9)); \S2_IBUF[10]\: IBUF port map ( O => S2_C(10), I => s2(10)); \S2_IBUF[11]\: IBUF port map ( O => S2_C(11), I => s2(11)); \S2_IBUF[12]\: IBUF port map ( O => S2_C(12), I => s2(12)); \S2_IBUF[13]\: IBUF port map ( O => S2_C(13), I => s2(13)); \S2_IBUF[14]\: IBUF port map ( O => S2_C(14), I => s2(14)); \S2_IBUF[15]\: IBUF port map ( O => S2_C(15), I => s2(15)); \S2_IBUF[16]\: IBUF port map ( O => S2_C(16), I => s2(16)); \S2_IBUF[17]\: IBUF port map ( O => S2_C(17), I => s2(17)); \S2_IBUF[18]\: IBUF port map ( O => S2_C(18), I => s2(18)); \S2_IBUF[19]\: IBUF port map ( O => S2_C(19), I => s2(19)); \S2_IBUF[20]\: IBUF port map ( O => S2_C(20), I => s2(20)); \S2_IBUF[21]\: IBUF port map ( O => S2_C(21), I => s2(21)); \S2_IBUF[22]\: IBUF port map ( O => S2_C(22), I => s2(22)); \S2_IBUF[23]\: IBUF port map ( O => S2_C(23), I => s2(23)); \S2_IBUF[24]\: IBUF port map ( O => S2_C(24), I => s2(24)); \S2_IBUF[25]\: IBUF port map ( O => S2_C(25), I => s2(25)); \S2_IBUF[26]\: IBUF port map ( O => S2_C(26), I => s2(26)); \S2_IBUF[27]\: IBUF port map ( O => S2_C(27), I => s2(27)); \S2_IBUF[28]\: IBUF port map ( O => S2_C(28), I => s2(28)); \S2_IBUF[29]\: IBUF port map ( O => S2_C(29), I => s2(29)); \S2_IBUF[30]\: IBUF port map ( O => S2_C(30), I => s2(30)); \S2_IBUF[31]\: IBUF port map ( O => S2_C(31), I => s2(31)); \A_CONFIG_IBUF[0]\: IBUF port map ( O => A_CONFIG_C(0), I => a_config(0)); \A_CONFIG_IBUF[1]\: IBUF port map ( O => A_CONFIG_C(1), I => a_config(1)); \A_CONFIG_IBUF[2]\: IBUF port map ( O => A_CONFIG_C(2), I => a_config(2)); \A_CONFIG_IBUF[3]\: IBUF port map ( O => A_CONFIG_C(3), I => a_config(3)); \M_CONFIG_IBUF[0]\: IBUF port map ( O => M_CONFIG_C(0), I => m_config(0)); \M_CONFIG_IBUF[1]\: IBUF port map ( O => M_CONFIG_C(1), I => m_config(1)); \M_CONFIG_IBUF[2]\: IBUF port map ( O => M_CONFIG_C(2), I => m_config(2)); \M_CONFIG_IBUF[3]\: IBUF port map ( O => M_CONFIG_C(3), I => m_config(3)); \S1OUT_OBUF[0]\: OBUF port map ( O => s1out(0), I => S1OUT_C(0)); \S1OUT_OBUF[1]\: OBUF port map ( O => s1out(1), I => S1OUT_C(1)); \S1OUT_OBUF[2]\: OBUF port map ( O => s1out(2), I => S1OUT_C(2)); \S1OUT_OBUF[3]\: OBUF port map ( O => s1out(3), I => S1OUT_C(3)); \S1OUT_OBUF[4]\: OBUF port map ( O => s1out(4), I => S1OUT_C(4)); \S1OUT_OBUF[5]\: OBUF port map ( O => s1out(5), I => S1OUT_C(5)); \S1OUT_OBUF[6]\: OBUF port map ( O => s1out(6), I => S1OUT_C(6)); \S1OUT_OBUF[7]\: OBUF port map ( O => s1out(7), I => S1OUT_C(7)); \S1OUT_OBUF[8]\: OBUF port map ( O => s1out(8), I => S1OUT_C(8)); \S1OUT_OBUF[9]\: OBUF port map ( O => s1out(9), I => S1OUT_C(9)); \S1OUT_OBUF[10]\: OBUF port map ( O => s1out(10), I => S1OUT_C(10)); \S1OUT_OBUF[11]\: OBUF port map ( O => s1out(11), I => S1OUT_C(11)); \S1OUT_OBUF[12]\: OBUF port map ( O => s1out(12), I => S1OUT_C(12)); \S1OUT_OBUF[13]\: OBUF port map ( O => s1out(13), I => S1OUT_C(13)); \S1OUT_OBUF[14]\: OBUF port map ( O => s1out(14), I => S1OUT_C(14)); \S1OUT_OBUF[15]\: OBUF port map ( O => s1out(15), I => S1OUT_C(15)); \S1OUT_OBUF[16]\: OBUF port map ( O => s1out(16), I => S1OUT_C(16)); \S1OUT_OBUF[17]\: OBUF port map ( O => s1out(17), I => S1OUT_C(17)); \S1OUT_OBUF[18]\: OBUF port map ( O => s1out(18), I => S1OUT_C(18)); \S1OUT_OBUF[19]\: OBUF port map ( O => s1out(19), I => S1OUT_C(19)); \S1OUT_OBUF[20]\: OBUF port map ( O => s1out(20), I => S1OUT_C(20)); \S1OUT_OBUF[21]\: OBUF port map ( O => s1out(21), I => S1OUT_C(21)); \S1OUT_OBUF[22]\: OBUF port map ( O => s1out(22), I => S1OUT_C(22)); \S1OUT_OBUF[23]\: OBUF port map ( O => s1out(23), I => S1OUT_C(23)); \S1OUT_OBUF[24]\: OBUF port map ( O => s1out(24), I => S1OUT_C(24)); \S1OUT_OBUF[25]\: OBUF port map ( O => s1out(25), I => S1OUT_C(25)); \S1OUT_OBUF[26]\: OBUF port map ( O => s1out(26), I => S1OUT_C(26)); \S1OUT_OBUF[27]\: OBUF port map ( O => s1out(27), I => S1OUT_C(27)); \S1OUT_OBUF[28]\: OBUF port map ( O => s1out(28), I => S1OUT_C(28)); \S1OUT_OBUF[29]\: OBUF port map ( O => s1out(29), I => S1OUT_C(29)); \S1OUT_OBUF[30]\: OBUF port map ( O => s1out(30), I => S1OUT_C(30)); \S1OUT_OBUF[31]\: OBUF port map ( O => s1out(31), I => S1OUT_C(31)); \S2OUT_OBUF[0]\: OBUF port map ( O => s2out(0), I => S2OUT_C(0)); \S2OUT_OBUF[1]\: OBUF port map ( O => s2out(1), I => S2OUT_C(1)); \S2OUT_OBUF[2]\: OBUF port map ( O => s2out(2), I => S2OUT_C(2)); \S2OUT_OBUF[3]\: OBUF port map ( O => s2out(3), I => S2OUT_C(3)); \S2OUT_OBUF[4]\: OBUF port map ( O => s2out(4), I => S2OUT_C(4)); \S2OUT_OBUF[5]\: OBUF port map ( O => s2out(5), I => S2OUT_C(5)); \S2OUT_OBUF[6]\: OBUF port map ( O => s2out(6), I => S2OUT_C(6)); \S2OUT_OBUF[7]\: OBUF port map ( O => s2out(7), I => S2OUT_C(7)); \S2OUT_OBUF[8]\: OBUF port map ( O => s2out(8), I => S2OUT_C(8)); \S2OUT_OBUF[9]\: OBUF port map ( O => s2out(9), I => S2OUT_C(9)); \S2OUT_OBUF[10]\: OBUF port map ( O => s2out(10), I => S2OUT_C(10)); \S2OUT_OBUF[11]\: OBUF port map ( O => s2out(11), I => S2OUT_C(11)); \S2OUT_OBUF[12]\: OBUF port map ( O => s2out(12), I => S2OUT_C(12)); \S2OUT_OBUF[13]\: OBUF port map ( O => s2out(13), I => S2OUT_C(13)); \S2OUT_OBUF[14]\: OBUF port map ( O => s2out(14), I => S2OUT_C(14)); \S2OUT_OBUF[15]\: OBUF port map ( O => s2out(15), I => S2OUT_C(15)); \S2OUT_OBUF[16]\: OBUF port map ( O => s2out(16), I => S2OUT_C(16)); \S2OUT_OBUF[17]\: OBUF port map ( O => s2out(17), I => S2OUT_C(17)); \S2OUT_OBUF[18]\: OBUF port map ( O => s2out(18), I => S2OUT_C(18)); \S2OUT_OBUF[19]\: OBUF port map ( O => s2out(19), I => S2OUT_C(19)); \S2OUT_OBUF[20]\: OBUF port map ( O => s2out(20), I => S2OUT_C(20)); \S2OUT_OBUF[21]\: OBUF port map ( O => s2out(21), I => S2OUT_C(21)); \S2OUT_OBUF[22]\: OBUF port map ( O => s2out(22), I => S2OUT_C(22)); \S2OUT_OBUF[23]\: OBUF port map ( O => s2out(23), I => S2OUT_C(23)); \S2OUT_OBUF[24]\: OBUF port map ( O => s2out(24), I => S2OUT_C(24)); \S2OUT_OBUF[25]\: OBUF port map ( O => s2out(25), I => S2OUT_C(25)); \S2OUT_OBUF[26]\: OBUF port map ( O => s2out(26), I => S2OUT_C(26)); \S2OUT_OBUF[27]\: OBUF port map ( O => s2out(27), I => S2OUT_C(27)); \S2OUT_OBUF[28]\: OBUF port map ( O => s2out(28), I => S2OUT_C(28)); \S2OUT_OBUF[29]\: OBUF port map ( O => s2out(29), I => S2OUT_C(29)); \S2OUT_OBUF[30]\: OBUF port map ( O => s2out(30), I => S2OUT_C(30)); \S2OUT_OBUF[31]\: OBUF port map ( O => s2out(31), I => S2OUT_C(31)); \A_STATUS_OBUF[0]\: OBUF port map ( O => a_status(0), I => A_STATUS_2(0)); \A_STATUS_OBUF[1]\: OBUF port map ( O => a_status(1), I => A_STATUS_2(1)); \A_STATUS_OBUF[2]\: OBUF port map ( O => a_status(2), I => A_STATUS_2(2)); \A_STATUS_OBUF[3]\: OBUF port map ( O => a_status(3), I => A_STATUS_2(3)); \A_STATUS_OBUF[4]\: OBUF port map ( O => a_status(4), I => A_STATUS_2(4)); \A_STATUS_OBUF[5]\: OBUF port map ( O => a_status(5), I => A_STATUS_2(5)); \A_STATUS_OBUF[6]\: OBUF port map ( O => a_status(6), I => A_STATUS_2(6)); \A_STATUS_OBUF[7]\: OBUF port map ( O => a_status(7), I => A_STATUS_1(7)); \A_STATUS_OBUF[8]\: OBUF port map ( O => a_status(8), I => A_STATUS_1(8)); \A_STATUS_OBUF[9]\: OBUF port map ( O => a_status(9), I => A_STATUS_1(9)); \A_STATUS_OBUF[10]\: OBUF port map ( O => a_status(10), I => A_STATUS_1(10)); \A_STATUS_OBUF[11]\: OBUF port map ( O => a_status(11), I => A_STATUS_1(11)); \A_STATUS_OBUF[12]\: OBUF port map ( O => a_status(12), I => A_STATUS_1(12)); \A_STATUS_OBUF[13]\: OBUF port map ( O => a_status(13), I => A_STATUS_1(13)); \A_STATUS_OBUF[14]\: OBUF port map ( O => a_status(14), I => A_STATUS_1(14)); \A_STATUS_OBUF[15]\: OBUF port map ( O => a_status(15), I => A_STATUS_1(15)); \A_STATUS_OBUF[16]\: OBUF port map ( O => a_status(16), I => A_STATUS_1(16)); \A_STATUS_OBUF[17]\: OBUF port map ( O => a_status(17), I => A_STATUS_1(17)); \A_STATUS_OBUF[18]\: OBUF port map ( O => a_status(18), I => A_STATUS_1(18)); \A_STATUS_OBUF[19]\: OBUF port map ( O => a_status(19), I => A_STATUS_1(19)); \A_STATUS_OBUF[20]\: OBUF port map ( O => a_status(20), I => A_STATUS_1(20)); \A_STATUS_OBUF[21]\: OBUF port map ( O => a_status(21), I => A_STATUS_1(21)); \A_STATUS_OBUF[22]\: OBUF port map ( O => a_status(22), I => A_STATUS_1(22)); \A_STATUS_OBUF[23]\: OBUF port map ( O => a_status(23), I => A_STATUS_1(23)); \A_STATUS_OBUF[24]\: OBUF port map ( O => a_status(24), I => A_STATUS_1(24)); \A_STATUS_OBUF[25]\: OBUF port map ( O => a_status(25), I => A_STATUS_1(25)); \A_STATUS_OBUF[26]\: OBUF port map ( O => a_status(26), I => A_STATUS_1(26)); \A_STATUS_OBUF[27]\: OBUF port map ( O => a_status(27), I => A_STATUS_1(27)); \M_STATUS_OBUF[0]\: OBUF port map ( O => m_status(0), I => M_STATUS_2(0)); \M_STATUS_OBUF[1]\: OBUF port map ( O => m_status(1), I => M_STATUS_2(1)); \M_STATUS_OBUF[2]\: OBUF port map ( O => m_status(2), I => M_STATUS_2(2)); \M_STATUS_OBUF[3]\: OBUF port map ( O => m_status(3), I => M_STATUS_2(3)); \M_STATUS_OBUF[4]\: OBUF port map ( O => m_status(4), I => M_STATUS_2(4)); \M_STATUS_OBUF[5]\: OBUF port map ( O => m_status(5), I => M_STATUS_2(5)); \M_STATUS_OBUF[6]\: OBUF port map ( O => m_status(6), I => M_STATUS_2(6)); \M_STATUS_OBUF[7]\: OBUF port map ( O => m_status(7), I => M_STATUS_1(7)); \M_STATUS_OBUF[8]\: OBUF port map ( O => m_status(8), I => M_STATUS_1(8)); \M_STATUS_OBUF[9]\: OBUF port map ( O => m_status(9), I => M_STATUS_1(9)); \M_STATUS_OBUF[10]\: OBUF port map ( O => m_status(10), I => M_STATUS_1(10)); \M_STATUS_OBUF[11]\: OBUF port map ( O => m_status(11), I => M_STATUS_1(11)); \M_STATUS_OBUF[12]\: OBUF port map ( O => m_status(12), I => M_STATUS_1(12)); \M_STATUS_OBUF[13]\: OBUF port map ( O => m_status(13), I => M_STATUS_1(13)); \M_STATUS_OBUF[14]\: OBUF port map ( O => m_status(14), I => M_STATUS_1(14)); \M_STATUS_OBUF[15]\: OBUF port map ( O => m_status(15), I => M_STATUS_1(15)); \M_STATUS_OBUF[16]\: OBUF port map ( O => m_status(16), I => M_STATUS_1(16)); \M_STATUS_OBUF[17]\: OBUF port map ( O => m_status(17), I => M_STATUS_1(17)); \M_STATUS_OBUF[18]\: OBUF port map ( O => m_status(18), I => M_STATUS_1(18)); \M_STATUS_OBUF[19]\: OBUF port map ( O => m_status(19), I => M_STATUS_1(19)); \M_STATUS_OBUF[20]\: OBUF port map ( O => m_status(20), I => M_STATUS_1(20)); \M_STATUS_OBUF[21]\: OBUF port map ( O => m_status(21), I => M_STATUS_1(21)); \M_STATUS_OBUF[22]\: OBUF port map ( O => m_status(22), I => M_STATUS_1(22)); \M_STATUS_OBUF[23]\: OBUF port map ( O => m_status(23), I => M_STATUS_1(23)); \M_STATUS_OBUF[24]\: OBUF port map ( O => m_status(24), I => M_STATUS_1(24)); \M_STATUS_OBUF[25]\: OBUF port map ( O => m_status(25), I => M_STATUS_1(25)); \M_STATUS_OBUF[26]\: OBUF port map ( O => m_status(26), I => M_STATUS_1(26)); \M_STATUS_OBUF[27]\: OBUF port map ( O => m_status(27), I => M_STATUS_1(27)); CLK_IBUF: BUFGP port map ( I => clk, O => CLK_C); WE_REG_Z1610: FD port map ( Q => WE_REG, D => WE_C, C => CLK_C); \S1_REG[9]_Z1611\: FD port map ( Q => S1_REG(9), D => S1_C(9), C => CLK_C); \S1_REG[8]_Z1612\: FD port map ( Q => S1_REG(8), D => S1_C(8), C => CLK_C); \S1_REG[7]_Z1613\: FD port map ( Q => S1_REG(7), D => S1_C(7), C => CLK_C); \S1_REG[6]_Z1614\: FD port map ( Q => S1_REG(6), D => S1_C(6), C => CLK_C); \S1_REG[5]_Z1615\: FD port map ( Q => S1_REG(5), D => S1_C(5), C => CLK_C); \S1_REG[4]_Z1616\: FD port map ( Q => S1_REG(4), D => S1_C(4), C => CLK_C); \S1_REG[3]_Z1617\: FD port map ( Q => S1_REG(3), D => S1_C(3), C => CLK_C); \S1_REG[2]_Z1618\: FD port map ( Q => S1_REG(2), D => S1_C(2), C => CLK_C); \S1_REG[1]_Z1619\: FD port map ( Q => S1_REG(1), D => S1_C(1), C => CLK_C); \S1_REG[0]_Z1620\: FD port map ( Q => S1_REG(0), D => S1_C(0), C => CLK_C); \S1_REG[24]_Z1621\: FD port map ( Q => S1_REG(24), D => S1_C(24), C => CLK_C); \S1_REG[23]_Z1622\: FD port map ( Q => S1_REG(23), D => S1_C(23), C => CLK_C); \S1_REG[22]_Z1623\: FD port map ( Q => S1_REG(22), D => S1_C(22), C => CLK_C); \S1_REG[21]_Z1624\: FD port map ( Q => S1_REG(21), D => S1_C(21), C => CLK_C); \S1_REG[20]_Z1625\: FD port map ( Q => S1_REG(20), D => S1_C(20), C => CLK_C); \S1_REG[19]_Z1626\: FD port map ( Q => S1_REG(19), D => S1_C(19), C => CLK_C); \S1_REG[18]_Z1627\: FD port map ( Q => S1_REG(18), D => S1_C(18), C => CLK_C); \S1_REG[17]_Z1628\: FD port map ( Q => S1_REG(17), D => S1_C(17), C => CLK_C); \S1_REG[16]_Z1629\: FD port map ( Q => S1_REG(16), D => S1_C(16), C => CLK_C); \S1_REG[15]_Z1630\: FD port map ( Q => S1_REG(15), D => S1_C(15), C => CLK_C); \S1_REG[14]_Z1631\: FD port map ( Q => S1_REG(14), D => S1_C(14), C => CLK_C); \S1_REG[13]_Z1632\: FD port map ( Q => S1_REG(13), D => S1_C(13), C => CLK_C); \S1_REG[12]_Z1633\: FD port map ( Q => S1_REG(12), D => S1_C(12), C => CLK_C); \S1_REG[11]_Z1634\: FD port map ( Q => S1_REG(11), D => S1_C(11), C => CLK_C); \S1_REG[10]_Z1635\: FD port map ( Q => S1_REG(10), D => S1_C(10), C => CLK_C); \S1OUT[7]_Z1636\: FD port map ( Q => S1OUT_C(7), D => ADD4(7), C => CLK_C); \S1OUT[6]_Z1637\: FD port map ( Q => S1OUT_C(6), D => ADD4(6), C => CLK_C); \S1OUT[5]_Z1638\: FD port map ( Q => S1OUT_C(5), D => ADD4(5), C => CLK_C); \S1OUT[4]_Z1639\: FD port map ( Q => S1OUT_C(4), D => ADD4(4), C => CLK_C); \S1OUT[3]_Z1640\: FD port map ( Q => S1OUT_C(3), D => ADD4(3), C => CLK_C); \S1OUT[2]_Z1641\: FD port map ( Q => S1OUT_C(2), D => ADD4(2), C => CLK_C); \S1OUT[1]_Z1642\: FD port map ( Q => S1OUT_C(1), D => ADD4(1), C => CLK_C); \S1OUT[0]_Z1643\: FD port map ( Q => S1OUT_C(0), D => ADD4(0), C => CLK_C); \S1_REG[31]_Z1644\: FD port map ( Q => S1_REG(31), D => S1_C(31), C => CLK_C); \S1_REG[30]_Z1645\: FD port map ( Q => S1_REG(30), D => S1_C(30), C => CLK_C); \S1_REG[29]_Z1646\: FD port map ( Q => S1_REG(29), D => S1_C(29), C => CLK_C); \S1_REG[28]_Z1647\: FD port map ( Q => S1_REG(28), D => S1_C(28), C => CLK_C); \S1_REG[27]_Z1648\: FD port map ( Q => S1_REG(27), D => S1_C(27), C => CLK_C); \S1_REG[26]_Z1649\: FD port map ( Q => S1_REG(26), D => S1_C(26), C => CLK_C); \S1_REG[25]_Z1650\: FD port map ( Q => S1_REG(25), D => S1_C(25), C => CLK_C); \S1OUT[22]_Z1651\: FD port map ( Q => S1OUT_C(22), D => ADD4(22), C => CLK_C); \S1OUT[21]_Z1652\: FD port map ( Q => S1OUT_C(21), D => ADD4(21), C => CLK_C); \S1OUT[20]_Z1653\: FD port map ( Q => S1OUT_C(20), D => ADD4(20), C => CLK_C); \S1OUT[19]_Z1654\: FD port map ( Q => S1OUT_C(19), D => ADD4(19), C => CLK_C); \S1OUT[18]_Z1655\: FD port map ( Q => S1OUT_C(18), D => ADD4(18), C => CLK_C); \S1OUT[17]_Z1656\: FD port map ( Q => S1OUT_C(17), D => ADD4(17), C => CLK_C); \S1OUT[16]_Z1657\: FD port map ( Q => S1OUT_C(16), D => ADD4(16), C => CLK_C); \S1OUT[15]_Z1658\: FD port map ( Q => S1OUT_C(15), D => ADD4(15), C => CLK_C); \S1OUT[14]_Z1659\: FD port map ( Q => S1OUT_C(14), D => ADD4(14), C => CLK_C); \S1OUT[13]_Z1660\: FD port map ( Q => S1OUT_C(13), D => ADD4(13), C => CLK_C); \S1OUT[12]_Z1661\: FD port map ( Q => S1OUT_C(12), D => ADD4(12), C => CLK_C); \S1OUT[11]_Z1662\: FD port map ( Q => S1OUT_C(11), D => ADD4(11), C => CLK_C); \S1OUT[10]_Z1663\: FD port map ( Q => S1OUT_C(10), D => ADD4(10), C => CLK_C); \S1OUT[9]_Z1664\: FD port map ( Q => S1OUT_C(9), D => ADD4(9), C => CLK_C); \S1OUT[8]_Z1665\: FD port map ( Q => S1OUT_C(8), D => ADD4(8), C => CLK_C); \S2_REG[5]_Z1666\: FD port map ( Q => S2_REG(5), D => S2_C(5), C => CLK_C); \S2_REG[4]_Z1667\: FD port map ( Q => S2_REG(4), D => S2_C(4), C => CLK_C); \S2_REG[3]_Z1668\: FD port map ( Q => S2_REG(3), D => S2_C(3), C => CLK_C); \S2_REG[2]_Z1669\: FD port map ( Q => S2_REG(2), D => S2_C(2), C => CLK_C); \S2_REG[1]_Z1670\: FD port map ( Q => S2_REG(1), D => S2_C(1), C => CLK_C); \S2_REG[0]_Z1671\: FD port map ( Q => S2_REG(0), D => S2_C(0), C => CLK_C); \S1OUT[31]_Z1672\: FD port map ( Q => S1OUT_C(31), D => ADD4(31), C => CLK_C); \S1OUT[30]_Z1673\: FD port map ( Q => S1OUT_C(30), D => ADD4(30), C => CLK_C); \S1OUT[29]_Z1674\: FD port map ( Q => S1OUT_C(29), D => ADD4(29), C => CLK_C); \S1OUT[28]_Z1675\: FD port map ( Q => S1OUT_C(28), D => ADD4(28), C => CLK_C); \S1OUT[27]_Z1676\: FD port map ( Q => S1OUT_C(27), D => ADD4(27), C => CLK_C); \S1OUT[26]_Z1677\: FD port map ( Q => S1OUT_C(26), D => ADD4(26), C => CLK_C); \S1OUT[25]_Z1678\: FD port map ( Q => S1OUT_C(25), D => ADD4(25), C => CLK_C); \S1OUT[24]_Z1679\: FD port map ( Q => S1OUT_C(24), D => ADD4(24), C => CLK_C); \S1OUT[23]_Z1680\: FD port map ( Q => S1OUT_C(23), D => ADD4(23), C => CLK_C); \S2_REG[20]_Z1681\: FD port map ( Q => S2_REG(20), D => S2_C(20), C => CLK_C); \S2_REG[19]_Z1682\: FD port map ( Q => S2_REG(19), D => S2_C(19), C => CLK_C); \S2_REG[18]_Z1683\: FD port map ( Q => S2_REG(18), D => S2_C(18), C => CLK_C); \S2_REG[17]_Z1684\: FD port map ( Q => S2_REG(17), D => S2_C(17), C => CLK_C); \S2_REG[16]_Z1685\: FD port map ( Q => S2_REG(16), D => S2_C(16), C => CLK_C); \S2_REG[15]_Z1686\: FD port map ( Q => S2_REG(15), D => S2_C(15), C => CLK_C); \S2_REG[14]_Z1687\: FD port map ( Q => S2_REG(14), D => S2_C(14), C => CLK_C); \S2_REG[13]_Z1688\: FD port map ( Q => S2_REG(13), D => S2_C(13), C => CLK_C); \S2_REG[12]_Z1689\: FD port map ( Q => S2_REG(12), D => S2_C(12), C => CLK_C); \S2_REG[11]_Z1690\: FD port map ( Q => S2_REG(11), D => S2_C(11), C => CLK_C); \S2_REG[10]_Z1691\: FD port map ( Q => S2_REG(10), D => S2_C(10), C => CLK_C); \S2_REG[9]_Z1692\: FD port map ( Q => S2_REG(9), D => S2_C(9), C => CLK_C); \S2_REG[8]_Z1693\: FD port map ( Q => S2_REG(8), D => S2_C(8), C => CLK_C); \S2_REG[7]_Z1694\: FD port map ( Q => S2_REG(7), D => S2_C(7), C => CLK_C); \S2_REG[6]_Z1695\: FD port map ( Q => S2_REG(6), D => S2_C(6), C => CLK_C); \S2OUT[3]_Z1696\: FD port map ( Q => S2OUT_C(3), D => ADD8(3), C => CLK_C); \S2OUT[2]_Z1697\: FD port map ( Q => S2OUT_C(2), D => ADD8(2), C => CLK_C); \S2OUT[1]_Z1698\: FD port map ( Q => S2OUT_C(1), D => ADD8(1), C => CLK_C); \S2OUT[0]_Z1699\: FD port map ( Q => S2OUT_C(0), D => ADD8(0), C => CLK_C); \S2_REG[31]_Z1700\: FD port map ( Q => S2_REG(31), D => S2_C(31), C => CLK_C); \S2_REG[30]_Z1701\: FD port map ( Q => S2_REG(30), D => S2_C(30), C => CLK_C); \S2_REG[29]_Z1702\: FD port map ( Q => S2_REG(29), D => S2_C(29), C => CLK_C); \S2_REG[28]_Z1703\: FD port map ( Q => S2_REG(28), D => S2_C(28), C => CLK_C); \S2_REG[27]_Z1704\: FD port map ( Q => S2_REG(27), D => S2_C(27), C => CLK_C); \S2_REG[26]_Z1705\: FD port map ( Q => S2_REG(26), D => S2_C(26), C => CLK_C); \S2_REG[25]_Z1706\: FD port map ( Q => S2_REG(25), D => S2_C(25), C => CLK_C); \S2_REG[24]_Z1707\: FD port map ( Q => S2_REG(24), D => S2_C(24), C => CLK_C); \S2_REG[23]_Z1708\: FD port map ( Q => S2_REG(23), D => S2_C(23), C => CLK_C); \S2_REG[22]_Z1709\: FD port map ( Q => S2_REG(22), D => S2_C(22), C => CLK_C); \S2_REG[21]_Z1710\: FD port map ( Q => S2_REG(21), D => S2_C(21), C => CLK_C); \S2OUT[18]_Z1711\: FD port map ( Q => S2OUT_C(18), D => ADD8(18), C => CLK_C); \S2OUT[17]_Z1712\: FD port map ( Q => S2OUT_C(17), D => ADD8(17), C => CLK_C); \S2OUT[16]_Z1713\: FD port map ( Q => S2OUT_C(16), D => ADD8(16), C => CLK_C); \S2OUT[15]_Z1714\: FD port map ( Q => S2OUT_C(15), D => ADD8(15), C => CLK_C); \S2OUT[14]_Z1715\: FD port map ( Q => S2OUT_C(14), D => ADD8(14), C => CLK_C); \S2OUT[13]_Z1716\: FD port map ( Q => S2OUT_C(13), D => ADD8(13), C => CLK_C); \S2OUT[12]_Z1717\: FD port map ( Q => S2OUT_C(12), D => ADD8(12), C => CLK_C); \S2OUT[11]_Z1718\: FD port map ( Q => S2OUT_C(11), D => ADD8(11), C => CLK_C); \S2OUT[10]_Z1719\: FD port map ( Q => S2OUT_C(10), D => ADD8(10), C => CLK_C); \S2OUT[9]_Z1720\: FD port map ( Q => S2OUT_C(9), D => ADD8(9), C => CLK_C); \S2OUT[8]_Z1721\: FD port map ( Q => S2OUT_C(8), D => ADD8(8), C => CLK_C); \S2OUT[7]_Z1722\: FD port map ( Q => S2OUT_C(7), D => ADD8(7), C => CLK_C); \S2OUT[6]_Z1723\: FD port map ( Q => S2OUT_C(6), D => ADD8(6), C => CLK_C); \S2OUT[5]_Z1724\: FD port map ( Q => S2OUT_C(5), D => ADD8(5), C => CLK_C); \S2OUT[4]_Z1725\: FD port map ( Q => S2OUT_C(4), D => ADD8(4), C => CLK_C); \A_CONFIG_REG[1]_Z1726\: FD port map ( Q => A_CONFIG_REG(1), D => A_CONFIG_C(1), C => CLK_C); \A_CONFIG_REG[0]_Z1727\: FD port map ( Q => A_CONFIG_REG(0), D => A_CONFIG_C(0), C => CLK_C); \S2OUT[31]_Z1728\: FD port map ( Q => S2OUT_C(31), D => ADD8(31), C => CLK_C); \S2OUT[30]_Z1729\: FD port map ( Q => S2OUT_C(30), D => ADD8(30), C => CLK_C); \S2OUT[29]_Z1730\: FD port map ( Q => S2OUT_C(29), D => ADD8(29), C => CLK_C); \S2OUT[28]_Z1731\: FD port map ( Q => S2OUT_C(28), D => ADD8(28), C => CLK_C); \S2OUT[27]_Z1732\: FD port map ( Q => S2OUT_C(27), D => ADD8(27), C => CLK_C); \S2OUT[26]_Z1733\: FD port map ( Q => S2OUT_C(26), D => ADD8(26), C => CLK_C); \S2OUT[25]_Z1734\: FD port map ( Q => S2OUT_C(25), D => ADD8(25), C => CLK_C); \S2OUT[24]_Z1735\: FD port map ( Q => S2OUT_C(24), D => ADD8(24), C => CLK_C); \S2OUT[23]_Z1736\: FD port map ( Q => S2OUT_C(23), D => ADD8(23), C => CLK_C); \S2OUT[22]_Z1737\: FD port map ( Q => S2OUT_C(22), D => ADD8(22), C => CLK_C); \S2OUT[21]_Z1738\: FD port map ( Q => S2OUT_C(21), D => ADD8(21), C => CLK_C); \S2OUT[20]_Z1739\: FD port map ( Q => S2OUT_C(20), D => ADD8(20), C => CLK_C); \S2OUT[19]_Z1740\: FD port map ( Q => S2OUT_C(19), D => ADD8(19), C => CLK_C); \COS_REG[8]_Z1741\: FD port map ( Q => COS_REG(8), D => COS_C(8), C => CLK_C); \COS_REG[7]_Z1742\: FD port map ( Q => COS_REG(7), D => COS_C(7), C => CLK_C); \COS_REG[6]_Z1743\: FD port map ( Q => COS_REG(6), D => COS_C(6), C => CLK_C); \COS_REG[5]_Z1744\: FD port map ( Q => COS_REG(5), D => COS_C(5), C => CLK_C); \COS_REG[4]_Z1745\: FD port map ( Q => COS_REG(4), D => COS_C(4), C => CLK_C); \COS_REG[3]_Z1746\: FD port map ( Q => COS_REG(3), D => COS_C(3), C => CLK_C); \COS_REG[2]_Z1747\: FD port map ( Q => COS_REG(2), D => COS_C(2), C => CLK_C); \COS_REG[1]_Z1748\: FD port map ( Q => COS_REG(1), D => COS_C(1), C => CLK_C); \COS_REG[0]_Z1749\: FD port map ( Q => COS_REG(0), D => COS_C(0), C => CLK_C); \M_CONFIG_REG[3]_Z1750\: FD port map ( Q => M_CONFIG_REG(3), D => M_CONFIG_C(3), C => CLK_C); \M_CONFIG_REG[2]_Z1751\: FD port map ( Q => M_CONFIG_REG(2), D => M_CONFIG_C(2), C => CLK_C); \M_CONFIG_REG[1]_Z1752\: FD port map ( Q => M_CONFIG_REG(1), D => M_CONFIG_C(1), C => CLK_C); \M_CONFIG_REG[0]_Z1753\: FD port map ( Q => M_CONFIG_REG(0), D => M_CONFIG_C(0), C => CLK_C); \A_CONFIG_REG[3]_Z1754\: FD port map ( Q => A_CONFIG_REG(3), D => A_CONFIG_C(3), C => CLK_C); \A_CONFIG_REG[2]_Z1755\: FD port map ( Q => A_CONFIG_REG(2), D => A_CONFIG_C(2), C => CLK_C); \COS_REG[23]_Z1756\: FD port map ( Q => COS_REG(23), D => COS_C(23), C => CLK_C); \COS_REG[22]_Z1757\: FD port map ( Q => COS_REG(22), D => COS_C(22), C => CLK_C); \COS_REG[21]_Z1758\: FD port map ( Q => COS_REG(21), D => COS_C(21), C => CLK_C); \COS_REG[20]_Z1759\: FD port map ( Q => COS_REG(20), D => COS_C(20), C => CLK_C); \COS_REG[19]_Z1760\: FD port map ( Q => COS_REG(19), D => COS_C(19), C => CLK_C); \COS_REG[18]_Z1761\: FD port map ( Q => COS_REG(18), D => COS_C(18), C => CLK_C); \COS_REG[17]_Z1762\: FD port map ( Q => COS_REG(17), D => COS_C(17), C => CLK_C); \COS_REG[16]_Z1763\: FD port map ( Q => COS_REG(16), D => COS_C(16), C => CLK_C); \COS_REG[15]_Z1764\: FD port map ( Q => COS_REG(15), D => COS_C(15), C => CLK_C); \COS_REG[14]_Z1765\: FD port map ( Q => COS_REG(14), D => COS_C(14), C => CLK_C); \COS_REG[13]_Z1766\: FD port map ( Q => COS_REG(13), D => COS_C(13), C => CLK_C); \COS_REG[12]_Z1767\: FD port map ( Q => COS_REG(12), D => COS_C(12), C => CLK_C); \COS_REG[11]_Z1768\: FD port map ( Q => COS_REG(11), D => COS_C(11), C => CLK_C); \COS_REG[10]_Z1769\: FD port map ( Q => COS_REG(10), D => COS_C(10), C => CLK_C); \COS_REG[9]_Z1770\: FD port map ( Q => COS_REG(9), D => COS_C(9), C => CLK_C); \ONE_REG[6]_Z1771\: FD port map ( Q => ONE_REG(6), D => ONE_C(6), C => CLK_C); \ONE_REG[5]_Z1772\: FD port map ( Q => ONE_REG(5), D => ONE_C(5), C => CLK_C); \ONE_REG[4]_Z1773\: FD port map ( Q => ONE_REG(4), D => ONE_C(4), C => CLK_C); \ONE_REG[3]_Z1774\: FD port map ( Q => ONE_REG(3), D => ONE_C(3), C => CLK_C); \ONE_REG[2]_Z1775\: FD port map ( Q => ONE_REG(2), D => ONE_C(2), C => CLK_C); \ONE_REG[1]_Z1776\: FD port map ( Q => ONE_REG(1), D => ONE_C(1), C => CLK_C); \ONE_REG[0]_Z1777\: FD port map ( Q => ONE_REG(0), D => ONE_C(0), C => CLK_C); \COS_REG[31]_Z1778\: FD port map ( Q => COS_REG(31), D => COS_C(31), C => CLK_C); \COS_REG[30]_Z1779\: FD port map ( Q => COS_REG(30), D => COS_C(30), C => CLK_C); \COS_REG[29]_Z1780\: FD port map ( Q => COS_REG(29), D => COS_C(29), C => CLK_C); \COS_REG[28]_Z1781\: FD port map ( Q => COS_REG(28), D => COS_C(28), C => CLK_C); \COS_REG[27]_Z1782\: FD port map ( Q => COS_REG(27), D => COS_C(27), C => CLK_C); \COS_REG[26]_Z1783\: FD port map ( Q => COS_REG(26), D => COS_C(26), C => CLK_C); \COS_REG[25]_Z1784\: FD port map ( Q => COS_REG(25), D => COS_C(25), C => CLK_C); \COS_REG[24]_Z1785\: FD port map ( Q => COS_REG(24), D => COS_C(24), C => CLK_C); \ONE_REG[21]_Z1786\: FD port map ( Q => ONE_REG(21), D => ONE_C(21), C => CLK_C); \ONE_REG[20]_Z1787\: FD port map ( Q => ONE_REG(20), D => ONE_C(20), C => CLK_C); \ONE_REG[19]_Z1788\: FD port map ( Q => ONE_REG(19), D => ONE_C(19), C => CLK_C); \ONE_REG[18]_Z1789\: FD port map ( Q => ONE_REG(18), D => ONE_C(18), C => CLK_C); \ONE_REG[17]_Z1790\: FD port map ( Q => ONE_REG(17), D => ONE_C(17), C => CLK_C); \ONE_REG[16]_Z1791\: FD port map ( Q => ONE_REG(16), D => ONE_C(16), C => CLK_C); \ONE_REG[15]_Z1792\: FD port map ( Q => ONE_REG(15), D => ONE_C(15), C => CLK_C); \ONE_REG[14]_Z1793\: FD port map ( Q => ONE_REG(14), D => ONE_C(14), C => CLK_C); \ONE_REG[13]_Z1794\: FD port map ( Q => ONE_REG(13), D => ONE_C(13), C => CLK_C); \ONE_REG[12]_Z1795\: FD port map ( Q => ONE_REG(12), D => ONE_C(12), C => CLK_C); \ONE_REG[11]_Z1796\: FD port map ( Q => ONE_REG(11), D => ONE_C(11), C => CLK_C); \ONE_REG[10]_Z1797\: FD port map ( Q => ONE_REG(10), D => ONE_C(10), C => CLK_C); \ONE_REG[9]_Z1798\: FD port map ( Q => ONE_REG(9), D => ONE_C(9), C => CLK_C); \ONE_REG[8]_Z1799\: FD port map ( Q => ONE_REG(8), D => ONE_C(8), C => CLK_C); \ONE_REG[7]_Z1800\: FD port map ( Q => ONE_REG(7), D => ONE_C(7), C => CLK_C); \ONE_REG[31]_Z1801\: FD port map ( Q => ONE_REG(31), D => ONE_C(31), C => CLK_C); \ONE_REG[30]_Z1802\: FD port map ( Q => ONE_REG(30), D => ONE_C(30), C => CLK_C); \ONE_REG[29]_Z1803\: FD port map ( Q => ONE_REG(29), D => ONE_C(29), C => CLK_C); \ONE_REG[28]_Z1804\: FD port map ( Q => ONE_REG(28), D => ONE_C(28), C => CLK_C); \ONE_REG[27]_Z1805\: FD port map ( Q => ONE_REG(27), D => ONE_C(27), C => CLK_C); \ONE_REG[26]_Z1806\: FD port map ( Q => ONE_REG(26), D => ONE_C(26), C => CLK_C); \ONE_REG[25]_Z1807\: FD port map ( Q => ONE_REG(25), D => ONE_C(25), C => CLK_C); \ONE_REG[24]_Z1808\: FD port map ( Q => ONE_REG(24), D => ONE_C(24), C => CLK_C); \ONE_REG[23]_Z1809\: FD port map ( Q => ONE_REG(23), D => ONE_C(23), C => CLK_C); \ONE_REG[22]_Z1810\: FD port map ( Q => ONE_REG(22), D => ONE_C(22), C => CLK_C); \X7_REG1[0]_Z1811\: FD port map ( Q => X7_REG1(0), D => X7_1(0), C => CLK_C); \X7_REG2[0]_Z1812\: FD port map ( Q => X7_REG2(0), D => X7_REG1(0), C => CLK_C); \X7_REG3[0]_Z1813\: FD port map ( Q => X7_REG3(0), D => X7_REG2(0), C => CLK_C); \X7_REG4[0]_Z1814\: FD port map ( Q => X7_REG4(0), D => X7_REG3(0), C => CLK_C); \X7_REG5[0]_Z1815\: FD port map ( Q => X7_REG5(0), D => X7_REG4(0), C => CLK_C); \X7_REG6[0]\: FD port map ( Q => X7(0), D => X7_REG5(0), C => CLK_C); \X7_REG1[1]_Z1817\: FD port map ( Q => X7_REG1(1), D => X7_1(1), C => CLK_C); \X7_REG2[1]_Z1818\: FD port map ( Q => X7_REG2(1), D => X7_REG1(1), C => CLK_C); \X7_REG3[1]_Z1819\: FD port map ( Q => X7_REG3(1), D => X7_REG2(1), C => CLK_C); \X7_REG4[1]_Z1820\: FD port map ( Q => X7_REG4(1), D => X7_REG3(1), C => CLK_C); \X7_REG5[1]_Z1821\: FD port map ( Q => X7_REG5(1), D => X7_REG4(1), C => CLK_C); \X7_REG6[1]\: FD port map ( Q => X7(1), D => X7_REG5(1), C => CLK_C); \X7_REG1[2]_Z1823\: FD port map ( Q => X7_REG1(2), D => X7_1(2), C => CLK_C); \X7_REG2[2]_Z1824\: FD port map ( Q => X7_REG2(2), D => X7_REG1(2), C => CLK_C); \X7_REG3[2]_Z1825\: FD port map ( Q => X7_REG3(2), D => X7_REG2(2), C => CLK_C); \X7_REG4[2]_Z1826\: FD port map ( Q => X7_REG4(2), D => X7_REG3(2), C => CLK_C); \X7_REG5[2]_Z1827\: FD port map ( Q => X7_REG5(2), D => X7_REG4(2), C => CLK_C); \X7_REG6[2]\: FD port map ( Q => X7(2), D => X7_REG5(2), C => CLK_C); \X7_REG1[3]_Z1829\: FD port map ( Q => X7_REG1(3), D => X7_1(3), C => CLK_C); \X7_REG2[3]_Z1830\: FD port map ( Q => X7_REG2(3), D => X7_REG1(3), C => CLK_C); \X7_REG3[3]_Z1831\: FD port map ( Q => X7_REG3(3), D => X7_REG2(3), C => CLK_C); \X7_REG4[3]_Z1832\: FD port map ( Q => X7_REG4(3), D => X7_REG3(3), C => CLK_C); \X7_REG5[3]_Z1833\: FD port map ( Q => X7_REG5(3), D => X7_REG4(3), C => CLK_C); \X7_REG6[3]\: FD port map ( Q => X7(3), D => X7_REG5(3), C => CLK_C); \X7_REG1[4]_Z1835\: FD port map ( Q => X7_REG1(4), D => X7_1(4), C => CLK_C); \X7_REG2[4]_Z1836\: FD port map ( Q => X7_REG2(4), D => X7_REG1(4), C => CLK_C); \X7_REG3[4]_Z1837\: FD port map ( Q => X7_REG3(4), D => X7_REG2(4), C => CLK_C); \X7_REG4[4]_Z1838\: FD port map ( Q => X7_REG4(4), D => X7_REG3(4), C => CLK_C); \X7_REG5[4]_Z1839\: FD port map ( Q => X7_REG5(4), D => X7_REG4(4), C => CLK_C); \X7_REG6[4]\: FD port map ( Q => X7(4), D => X7_REG5(4), C => CLK_C); \X7_REG1[5]_Z1841\: FD port map ( Q => X7_REG1(5), D => X7_1(5), C => CLK_C); \X7_REG2[5]_Z1842\: FD port map ( Q => X7_REG2(5), D => X7_REG1(5), C => CLK_C); \X7_REG3[5]_Z1843\: FD port map ( Q => X7_REG3(5), D => X7_REG2(5), C => CLK_C); \X7_REG4[5]_Z1844\: FD port map ( Q => X7_REG4(5), D => X7_REG3(5), C => CLK_C); \X7_REG5[5]_Z1845\: FD port map ( Q => X7_REG5(5), D => X7_REG4(5), C => CLK_C); \X7_REG6[5]\: FD port map ( Q => X7(5), D => X7_REG5(5), C => CLK_C); \X7_REG1[6]_Z1847\: FD port map ( Q => X7_REG1(6), D => X7_1(6), C => CLK_C); \X7_REG2[6]_Z1848\: FD port map ( Q => X7_REG2(6), D => X7_REG1(6), C => CLK_C); \X7_REG3[6]_Z1849\: FD port map ( Q => X7_REG3(6), D => X7_REG2(6), C => CLK_C); \X7_REG4[6]_Z1850\: FD port map ( Q => X7_REG4(6), D => X7_REG3(6), C => CLK_C); \X7_REG5[6]_Z1851\: FD port map ( Q => X7_REG5(6), D => X7_REG4(6), C => CLK_C); \X7_REG6[6]\: FD port map ( Q => X7(6), D => X7_REG5(6), C => CLK_C); \X7_REG1[7]_Z1853\: FD port map ( Q => X7_REG1(7), D => X7_1(7), C => CLK_C); \X7_REG2[7]_Z1854\: FD port map ( Q => X7_REG2(7), D => X7_REG1(7), C => CLK_C); \X7_REG3[7]_Z1855\: FD port map ( Q => X7_REG3(7), D => X7_REG2(7), C => CLK_C); \X7_REG4[7]_Z1856\: FD port map ( Q => X7_REG4(7), D => X7_REG3(7), C => CLK_C); \X7_REG5[7]_Z1857\: FD port map ( Q => X7_REG5(7), D => X7_REG4(7), C => CLK_C); \X7_REG6[7]\: FD port map ( Q => X7(7), D => X7_REG5(7), C => CLK_C); \X7_REG1[8]_Z1859\: FD port map ( Q => X7_REG1(8), D => X7_1(8), C => CLK_C); \X7_REG2[8]_Z1860\: FD port map ( Q => X7_REG2(8), D => X7_REG1(8), C => CLK_C); \X7_REG3[8]_Z1861\: FD port map ( Q => X7_REG3(8), D => X7_REG2(8), C => CLK_C); \X7_REG4[8]_Z1862\: FD port map ( Q => X7_REG4(8), D => X7_REG3(8), C => CLK_C); \X7_REG5[8]_Z1863\: FD port map ( Q => X7_REG5(8), D => X7_REG4(8), C => CLK_C); \X7_REG6[8]\: FD port map ( Q => X7(8), D => X7_REG5(8), C => CLK_C); \X7_REG1[9]_Z1865\: FD port map ( Q => X7_REG1(9), D => X7_1(9), C => CLK_C); \X7_REG2[9]_Z1866\: FD port map ( Q => X7_REG2(9), D => X7_REG1(9), C => CLK_C); \X7_REG3[9]_Z1867\: FD port map ( Q => X7_REG3(9), D => X7_REG2(9), C => CLK_C); \X7_REG4[9]_Z1868\: FD port map ( Q => X7_REG4(9), D => X7_REG3(9), C => CLK_C); \X7_REG5[9]_Z1869\: FD port map ( Q => X7_REG5(9), D => X7_REG4(9), C => CLK_C); \X7_REG6[9]\: FD port map ( Q => X7(9), D => X7_REG5(9), C => CLK_C); \X7_REG1[10]_Z1871\: FD port map ( Q => X7_REG1(10), D => X7_1(10), C => CLK_C); \X7_REG2[10]_Z1872\: FD port map ( Q => X7_REG2(10), D => X7_REG1(10), C => CLK_C); \X7_REG3[10]_Z1873\: FD port map ( Q => X7_REG3(10), D => X7_REG2(10), C => CLK_C); \X7_REG4[10]_Z1874\: FD port map ( Q => X7_REG4(10), D => X7_REG3(10), C => CLK_C); \X7_REG5[10]_Z1875\: FD port map ( Q => X7_REG5(10), D => X7_REG4(10), C => CLK_C); \X7_REG6[10]\: FD port map ( Q => X7(10), D => X7_REG5(10), C => CLK_C); \X7_REG1[11]_Z1877\: FD port map ( Q => X7_REG1(11), D => X7_1(11), C => CLK_C); \X7_REG2[11]_Z1878\: FD port map ( Q => X7_REG2(11), D => X7_REG1(11), C => CLK_C); \X7_REG3[11]_Z1879\: FD port map ( Q => X7_REG3(11), D => X7_REG2(11), C => CLK_C); \X7_REG4[11]_Z1880\: FD port map ( Q => X7_REG4(11), D => X7_REG3(11), C => CLK_C); \X7_REG5[11]_Z1881\: FD port map ( Q => X7_REG5(11), D => X7_REG4(11), C => CLK_C); \X7_REG6[11]\: FD port map ( Q => X7(11), D => X7_REG5(11), C => CLK_C); \X7_REG1[12]_Z1883\: FD port map ( Q => X7_REG1(12), D => X7_1(12), C => CLK_C); \X7_REG2[12]_Z1884\: FD port map ( Q => X7_REG2(12), D => X7_REG1(12), C => CLK_C); \X7_REG3[12]_Z1885\: FD port map ( Q => X7_REG3(12), D => X7_REG2(12), C => CLK_C); \X7_REG4[12]_Z1886\: FD port map ( Q => X7_REG4(12), D => X7_REG3(12), C => CLK_C); \X7_REG5[12]_Z1887\: FD port map ( Q => X7_REG5(12), D => X7_REG4(12), C => CLK_C); \X7_REG6[12]\: FD port map ( Q => X7(12), D => X7_REG5(12), C => CLK_C); \X7_REG1[13]_Z1889\: FD port map ( Q => X7_REG1(13), D => X7_1(13), C => CLK_C); \X7_REG2[13]_Z1890\: FD port map ( Q => X7_REG2(13), D => X7_REG1(13), C => CLK_C); \X7_REG3[13]_Z1891\: FD port map ( Q => X7_REG3(13), D => X7_REG2(13), C => CLK_C); \X7_REG4[13]_Z1892\: FD port map ( Q => X7_REG4(13), D => X7_REG3(13), C => CLK_C); \X7_REG5[13]_Z1893\: FD port map ( Q => X7_REG5(13), D => X7_REG4(13), C => CLK_C); \X7_REG6[13]\: FD port map ( Q => X7(13), D => X7_REG5(13), C => CLK_C); \X7_REG1[14]_Z1895\: FD port map ( Q => X7_REG1(14), D => X7_1(14), C => CLK_C); \X7_REG2[14]_Z1896\: FD port map ( Q => X7_REG2(14), D => X7_REG1(14), C => CLK_C); \X7_REG3[14]_Z1897\: FD port map ( Q => X7_REG3(14), D => X7_REG2(14), C => CLK_C); \X7_REG4[14]_Z1898\: FD port map ( Q => X7_REG4(14), D => X7_REG3(14), C => CLK_C); \X7_REG5[14]_Z1899\: FD port map ( Q => X7_REG5(14), D => X7_REG4(14), C => CLK_C); \X7_REG6[14]\: FD port map ( Q => X7(14), D => X7_REG5(14), C => CLK_C); \X7_REG1[15]_Z1901\: FD port map ( Q => X7_REG1(15), D => X7_1(15), C => CLK_C); \X7_REG2[15]_Z1902\: FD port map ( Q => X7_REG2(15), D => X7_REG1(15), C => CLK_C); \X7_REG3[15]_Z1903\: FD port map ( Q => X7_REG3(15), D => X7_REG2(15), C => CLK_C); \X7_REG4[15]_Z1904\: FD port map ( Q => X7_REG4(15), D => X7_REG3(15), C => CLK_C); \X7_REG5[15]_Z1905\: FD port map ( Q => X7_REG5(15), D => X7_REG4(15), C => CLK_C); \X7_REG6[15]\: FD port map ( Q => X7(15), D => X7_REG5(15), C => CLK_C); \X7_REG1[16]_Z1907\: FD port map ( Q => X7_REG1(16), D => X7_1(16), C => CLK_C); \X7_REG2[16]_Z1908\: FD port map ( Q => X7_REG2(16), D => X7_REG1(16), C => CLK_C); \X7_REG3[16]_Z1909\: FD port map ( Q => X7_REG3(16), D => X7_REG2(16), C => CLK_C); \X7_REG4[16]_Z1910\: FD port map ( Q => X7_REG4(16), D => X7_REG3(16), C => CLK_C); \X7_REG5[16]_Z1911\: FD port map ( Q => X7_REG5(16), D => X7_REG4(16), C => CLK_C); \X7_REG6[16]\: FD port map ( Q => X7(16), D => X7_REG5(16), C => CLK_C); \X7_REG1[17]_Z1913\: FD port map ( Q => X7_REG1(17), D => X7_1(17), C => CLK_C); \X7_REG2[17]_Z1914\: FD port map ( Q => X7_REG2(17), D => X7_REG1(17), C => CLK_C); \X7_REG3[17]_Z1915\: FD port map ( Q => X7_REG3(17), D => X7_REG2(17), C => CLK_C); \X7_REG4[17]_Z1916\: FD port map ( Q => X7_REG4(17), D => X7_REG3(17), C => CLK_C); \X7_REG5[17]_Z1917\: FD port map ( Q => X7_REG5(17), D => X7_REG4(17), C => CLK_C); \X7_REG6[17]\: FD port map ( Q => X7(17), D => X7_REG5(17), C => CLK_C); \X7_REG1[18]_Z1919\: FD port map ( Q => X7_REG1(18), D => X7_1(18), C => CLK_C); \X7_REG2[18]_Z1920\: FD port map ( Q => X7_REG2(18), D => X7_REG1(18), C => CLK_C); \X7_REG3[18]_Z1921\: FD port map ( Q => X7_REG3(18), D => X7_REG2(18), C => CLK_C); \X7_REG4[18]_Z1922\: FD port map ( Q => X7_REG4(18), D => X7_REG3(18), C => CLK_C); \X7_REG5[18]_Z1923\: FD port map ( Q => X7_REG5(18), D => X7_REG4(18), C => CLK_C); \X7_REG6[18]\: FD port map ( Q => X7(18), D => X7_REG5(18), C => CLK_C); \X7_REG1[19]_Z1925\: FD port map ( Q => X7_REG1(19), D => X7_1(19), C => CLK_C); \X7_REG2[19]_Z1926\: FD port map ( Q => X7_REG2(19), D => X7_REG1(19), C => CLK_C); \X7_REG3[19]_Z1927\: FD port map ( Q => X7_REG3(19), D => X7_REG2(19), C => CLK_C); \X7_REG4[19]_Z1928\: FD port map ( Q => X7_REG4(19), D => X7_REG3(19), C => CLK_C); \X7_REG5[19]_Z1929\: FD port map ( Q => X7_REG5(19), D => X7_REG4(19), C => CLK_C); \X7_REG6[19]\: FD port map ( Q => X7(19), D => X7_REG5(19), C => CLK_C); \X7_REG1[20]_Z1931\: FD port map ( Q => X7_REG1(20), D => X7_1(20), C => CLK_C); \X7_REG2[20]_Z1932\: FD port map ( Q => X7_REG2(20), D => X7_REG1(20), C => CLK_C); \X7_REG3[20]_Z1933\: FD port map ( Q => X7_REG3(20), D => X7_REG2(20), C => CLK_C); \X7_REG4[20]_Z1934\: FD port map ( Q => X7_REG4(20), D => X7_REG3(20), C => CLK_C); \X7_REG5[20]_Z1935\: FD port map ( Q => X7_REG5(20), D => X7_REG4(20), C => CLK_C); \X7_REG6[20]\: FD port map ( Q => X7(20), D => X7_REG5(20), C => CLK_C); \X7_REG1[21]_Z1937\: FD port map ( Q => X7_REG1(21), D => X7_1(21), C => CLK_C); \X7_REG2[21]_Z1938\: FD port map ( Q => X7_REG2(21), D => X7_REG1(21), C => CLK_C); \X7_REG3[21]_Z1939\: FD port map ( Q => X7_REG3(21), D => X7_REG2(21), C => CLK_C); \X7_REG4[21]_Z1940\: FD port map ( Q => X7_REG4(21), D => X7_REG3(21), C => CLK_C); \X7_REG5[21]_Z1941\: FD port map ( Q => X7_REG5(21), D => X7_REG4(21), C => CLK_C); \X7_REG6[21]\: FD port map ( Q => X7(21), D => X7_REG5(21), C => CLK_C); \X7_REG1[22]_Z1943\: FD port map ( Q => X7_REG1(22), D => X7_1(22), C => CLK_C); \X7_REG2[22]_Z1944\: FD port map ( Q => X7_REG2(22), D => X7_REG1(22), C => CLK_C); \X7_REG3[22]_Z1945\: FD port map ( Q => X7_REG3(22), D => X7_REG2(22), C => CLK_C); \X7_REG4[22]_Z1946\: FD port map ( Q => X7_REG4(22), D => X7_REG3(22), C => CLK_C); \X7_REG5[22]_Z1947\: FD port map ( Q => X7_REG5(22), D => X7_REG4(22), C => CLK_C); \X7_REG6[22]\: FD port map ( Q => X7(22), D => X7_REG5(22), C => CLK_C); \X7_REG1[23]_Z1949\: FD port map ( Q => X7_REG1(23), D => X7_1(23), C => CLK_C); \X7_REG2[23]_Z1950\: FD port map ( Q => X7_REG2(23), D => X7_REG1(23), C => CLK_C); \X7_REG3[23]_Z1951\: FD port map ( Q => X7_REG3(23), D => X7_REG2(23), C => CLK_C); \X7_REG4[23]_Z1952\: FD port map ( Q => X7_REG4(23), D => X7_REG3(23), C => CLK_C); \X7_REG5[23]_Z1953\: FD port map ( Q => X7_REG5(23), D => X7_REG4(23), C => CLK_C); \X7_REG6[23]\: FD port map ( Q => X7(23), D => X7_REG5(23), C => CLK_C); \X7_REG1[24]_Z1955\: FD port map ( Q => X7_REG1(24), D => X7_1(24), C => CLK_C); \X7_REG2[24]_Z1956\: FD port map ( Q => X7_REG2(24), D => X7_REG1(24), C => CLK_C); \X7_REG3[24]_Z1957\: FD port map ( Q => X7_REG3(24), D => X7_REG2(24), C => CLK_C); \X7_REG4[24]_Z1958\: FD port map ( Q => X7_REG4(24), D => X7_REG3(24), C => CLK_C); \X7_REG5[24]_Z1959\: FD port map ( Q => X7_REG5(24), D => X7_REG4(24), C => CLK_C); \X7_REG6[24]\: FD port map ( Q => X7(24), D => X7_REG5(24), C => CLK_C); \X7_REG1[25]_Z1961\: FD port map ( Q => X7_REG1(25), D => X7_1(25), C => CLK_C); \X7_REG2[25]_Z1962\: FD port map ( Q => X7_REG2(25), D => X7_REG1(25), C => CLK_C); \X7_REG3[25]_Z1963\: FD port map ( Q => X7_REG3(25), D => X7_REG2(25), C => CLK_C); \X7_REG4[25]_Z1964\: FD port map ( Q => X7_REG4(25), D => X7_REG3(25), C => CLK_C); \X7_REG5[25]_Z1965\: FD port map ( Q => X7_REG5(25), D => X7_REG4(25), C => CLK_C); \X7_REG6[25]\: FD port map ( Q => X7(25), D => X7_REG5(25), C => CLK_C); \X7_REG1[26]_Z1967\: FD port map ( Q => X7_REG1(26), D => X7_1(26), C => CLK_C); \X7_REG2[26]_Z1968\: FD port map ( Q => X7_REG2(26), D => X7_REG1(26), C => CLK_C); \X7_REG3[26]_Z1969\: FD port map ( Q => X7_REG3(26), D => X7_REG2(26), C => CLK_C); \X7_REG4[26]_Z1970\: FD port map ( Q => X7_REG4(26), D => X7_REG3(26), C => CLK_C); \X7_REG5[26]_Z1971\: FD port map ( Q => X7_REG5(26), D => X7_REG4(26), C => CLK_C); \X7_REG6[26]\: FD port map ( Q => X7(26), D => X7_REG5(26), C => CLK_C); \X7_REG1[27]_Z1973\: FD port map ( Q => X7_REG1(27), D => X7_1(27), C => CLK_C); \X7_REG2[27]_Z1974\: FD port map ( Q => X7_REG2(27), D => X7_REG1(27), C => CLK_C); \X7_REG3[27]_Z1975\: FD port map ( Q => X7_REG3(27), D => X7_REG2(27), C => CLK_C); \X7_REG4[27]_Z1976\: FD port map ( Q => X7_REG4(27), D => X7_REG3(27), C => CLK_C); \X7_REG5[27]_Z1977\: FD port map ( Q => X7_REG5(27), D => X7_REG4(27), C => CLK_C); \X7_REG6[27]\: FD port map ( Q => X7(27), D => X7_REG5(27), C => CLK_C); \X7_REG1[28]_Z1979\: FD port map ( Q => X7_REG1(28), D => X7_1(28), C => CLK_C); \X7_REG2[28]_Z1980\: FD port map ( Q => X7_REG2(28), D => X7_REG1(28), C => CLK_C); \X7_REG3[28]_Z1981\: FD port map ( Q => X7_REG3(28), D => X7_REG2(28), C => CLK_C); \X7_REG4[28]_Z1982\: FD port map ( Q => X7_REG4(28), D => X7_REG3(28), C => CLK_C); \X7_REG5[28]_Z1983\: FD port map ( Q => X7_REG5(28), D => X7_REG4(28), C => CLK_C); \X7_REG6[28]\: FD port map ( Q => X7(28), D => X7_REG5(28), C => CLK_C); \X7_REG1[29]_Z1985\: FD port map ( Q => X7_REG1(29), D => X7_1(29), C => CLK_C); \X7_REG2[29]_Z1986\: FD port map ( Q => X7_REG2(29), D => X7_REG1(29), C => CLK_C); \X7_REG3[29]_Z1987\: FD port map ( Q => X7_REG3(29), D => X7_REG2(29), C => CLK_C); \X7_REG4[29]_Z1988\: FD port map ( Q => X7_REG4(29), D => X7_REG3(29), C => CLK_C); \X7_REG5[29]_Z1989\: FD port map ( Q => X7_REG5(29), D => X7_REG4(29), C => CLK_C); \X7_REG6[29]\: FD port map ( Q => X7(29), D => X7_REG5(29), C => CLK_C); \X7_REG1[30]_Z1991\: FD port map ( Q => X7_REG1(30), D => X7_1(30), C => CLK_C); \X7_REG2[30]_Z1992\: FD port map ( Q => X7_REG2(30), D => X7_REG1(30), C => CLK_C); \X7_REG3[30]_Z1993\: FD port map ( Q => X7_REG3(30), D => X7_REG2(30), C => CLK_C); \X7_REG4[30]_Z1994\: FD port map ( Q => X7_REG4(30), D => X7_REG3(30), C => CLK_C); \X7_REG5[30]_Z1995\: FD port map ( Q => X7_REG5(30), D => X7_REG4(30), C => CLK_C); \X7_REG6[30]\: FD port map ( Q => X7(30), D => X7_REG5(30), C => CLK_C); \X7_REG1[31]_Z1997\: FD port map ( Q => X7_REG1(31), D => X7_1(31), C => CLK_C); \X7_REG2[31]_Z1998\: FD port map ( Q => X7_REG2(31), D => X7_REG1(31), C => CLK_C); \X7_REG3[31]_Z1999\: FD port map ( Q => X7_REG3(31), D => X7_REG2(31), C => CLK_C); \X7_REG4[31]_Z2000\: FD port map ( Q => X7_REG4(31), D => X7_REG3(31), C => CLK_C); \X7_REG5[31]_Z2001\: FD port map ( Q => X7_REG5(31), D => X7_REG4(31), C => CLK_C); \X7_REG6[31]\: FD port map ( Q => X7(31), D => X7_REG5(31), C => CLK_C); \X3_REG1[0]_Z2003\: FD port map ( Q => X3_REG1(0), D => X3_1(0), C => CLK_C); \X3_REG2[0]_Z2004\: FD port map ( Q => X3_REG2(0), D => X3_REG1(0), C => CLK_C); \X3_REG3[0]_Z2005\: FD port map ( Q => X3_REG3(0), D => X3_REG2(0), C => CLK_C); \X3_REG4[0]_Z2006\: FD port map ( Q => X3_REG4(0), D => X3_REG3(0), C => CLK_C); \X3_REG5[0]_Z2007\: FD port map ( Q => X3_REG5(0), D => X3_REG4(0), C => CLK_C); \X3_REG6[0]\: FD port map ( Q => X3(0), D => X3_REG5(0), C => CLK_C); \X3_REG1[1]_Z2009\: FD port map ( Q => X3_REG1(1), D => X3_1(1), C => CLK_C); \X3_REG2[1]_Z2010\: FD port map ( Q => X3_REG2(1), D => X3_REG1(1), C => CLK_C); \X3_REG3[1]_Z2011\: FD port map ( Q => X3_REG3(1), D => X3_REG2(1), C => CLK_C); \X3_REG4[1]_Z2012\: FD port map ( Q => X3_REG4(1), D => X3_REG3(1), C => CLK_C); \X3_REG5[1]_Z2013\: FD port map ( Q => X3_REG5(1), D => X3_REG4(1), C => CLK_C); \X3_REG6[1]\: FD port map ( Q => X3(1), D => X3_REG5(1), C => CLK_C); \X3_REG1[2]_Z2015\: FD port map ( Q => X3_REG1(2), D => X3_1(2), C => CLK_C); \X3_REG2[2]_Z2016\: FD port map ( Q => X3_REG2(2), D => X3_REG1(2), C => CLK_C); \X3_REG3[2]_Z2017\: FD port map ( Q => X3_REG3(2), D => X3_REG2(2), C => CLK_C); \X3_REG4[2]_Z2018\: FD port map ( Q => X3_REG4(2), D => X3_REG3(2), C => CLK_C); \X3_REG5[2]_Z2019\: FD port map ( Q => X3_REG5(2), D => X3_REG4(2), C => CLK_C); \X3_REG6[2]\: FD port map ( Q => X3(2), D => X3_REG5(2), C => CLK_C); \X3_REG1[3]_Z2021\: FD port map ( Q => X3_REG1(3), D => X3_1(3), C => CLK_C); \X3_REG2[3]_Z2022\: FD port map ( Q => X3_REG2(3), D => X3_REG1(3), C => CLK_C); \X3_REG3[3]_Z2023\: FD port map ( Q => X3_REG3(3), D => X3_REG2(3), C => CLK_C); \X3_REG4[3]_Z2024\: FD port map ( Q => X3_REG4(3), D => X3_REG3(3), C => CLK_C); \X3_REG5[3]_Z2025\: FD port map ( Q => X3_REG5(3), D => X3_REG4(3), C => CLK_C); \X3_REG6[3]\: FD port map ( Q => X3(3), D => X3_REG5(3), C => CLK_C); \X3_REG1[4]_Z2027\: FD port map ( Q => X3_REG1(4), D => X3_1(4), C => CLK_C); \X3_REG2[4]_Z2028\: FD port map ( Q => X3_REG2(4), D => X3_REG1(4), C => CLK_C); \X3_REG3[4]_Z2029\: FD port map ( Q => X3_REG3(4), D => X3_REG2(4), C => CLK_C); \X3_REG4[4]_Z2030\: FD port map ( Q => X3_REG4(4), D => X3_REG3(4), C => CLK_C); \X3_REG5[4]_Z2031\: FD port map ( Q => X3_REG5(4), D => X3_REG4(4), C => CLK_C); \X3_REG6[4]\: FD port map ( Q => X3(4), D => X3_REG5(4), C => CLK_C); \X3_REG1[5]_Z2033\: FD port map ( Q => X3_REG1(5), D => X3_1(5), C => CLK_C); \X3_REG2[5]_Z2034\: FD port map ( Q => X3_REG2(5), D => X3_REG1(5), C => CLK_C); \X3_REG3[5]_Z2035\: FD port map ( Q => X3_REG3(5), D => X3_REG2(5), C => CLK_C); \X3_REG4[5]_Z2036\: FD port map ( Q => X3_REG4(5), D => X3_REG3(5), C => CLK_C); \X3_REG5[5]_Z2037\: FD port map ( Q => X3_REG5(5), D => X3_REG4(5), C => CLK_C); \X3_REG6[5]\: FD port map ( Q => X3(5), D => X3_REG5(5), C => CLK_C); \X3_REG1[6]_Z2039\: FD port map ( Q => X3_REG1(6), D => X3_1(6), C => CLK_C); \X3_REG2[6]_Z2040\: FD port map ( Q => X3_REG2(6), D => X3_REG1(6), C => CLK_C); \X3_REG3[6]_Z2041\: FD port map ( Q => X3_REG3(6), D => X3_REG2(6), C => CLK_C); \X3_REG4[6]_Z2042\: FD port map ( Q => X3_REG4(6), D => X3_REG3(6), C => CLK_C); \X3_REG5[6]_Z2043\: FD port map ( Q => X3_REG5(6), D => X3_REG4(6), C => CLK_C); \X3_REG6[6]\: FD port map ( Q => X3(6), D => X3_REG5(6), C => CLK_C); \X3_REG1[7]_Z2045\: FD port map ( Q => X3_REG1(7), D => X3_1(7), C => CLK_C); \X3_REG2[7]_Z2046\: FD port map ( Q => X3_REG2(7), D => X3_REG1(7), C => CLK_C); \X3_REG3[7]_Z2047\: FD port map ( Q => X3_REG3(7), D => X3_REG2(7), C => CLK_C); \X3_REG4[7]_Z2048\: FD port map ( Q => X3_REG4(7), D => X3_REG3(7), C => CLK_C); \X3_REG5[7]_Z2049\: FD port map ( Q => X3_REG5(7), D => X3_REG4(7), C => CLK_C); \X3_REG6[7]\: FD port map ( Q => X3(7), D => X3_REG5(7), C => CLK_C); \X3_REG1[8]_Z2051\: FD port map ( Q => X3_REG1(8), D => X3_1(8), C => CLK_C); \X3_REG2[8]_Z2052\: FD port map ( Q => X3_REG2(8), D => X3_REG1(8), C => CLK_C); \X3_REG3[8]_Z2053\: FD port map ( Q => X3_REG3(8), D => X3_REG2(8), C => CLK_C); \X3_REG4[8]_Z2054\: FD port map ( Q => X3_REG4(8), D => X3_REG3(8), C => CLK_C); \X3_REG5[8]_Z2055\: FD port map ( Q => X3_REG5(8), D => X3_REG4(8), C => CLK_C); \X3_REG6[8]\: FD port map ( Q => X3(8), D => X3_REG5(8), C => CLK_C); \X3_REG1[9]_Z2057\: FD port map ( Q => X3_REG1(9), D => X3_1(9), C => CLK_C); \X3_REG2[9]_Z2058\: FD port map ( Q => X3_REG2(9), D => X3_REG1(9), C => CLK_C); \X3_REG3[9]_Z2059\: FD port map ( Q => X3_REG3(9), D => X3_REG2(9), C => CLK_C); \X3_REG4[9]_Z2060\: FD port map ( Q => X3_REG4(9), D => X3_REG3(9), C => CLK_C); \X3_REG5[9]_Z2061\: FD port map ( Q => X3_REG5(9), D => X3_REG4(9), C => CLK_C); \X3_REG6[9]\: FD port map ( Q => X3(9), D => X3_REG5(9), C => CLK_C); \X3_REG1[10]_Z2063\: FD port map ( Q => X3_REG1(10), D => X3_1(10), C => CLK_C); \X3_REG2[10]_Z2064\: FD port map ( Q => X3_REG2(10), D => X3_REG1(10), C => CLK_C); \X3_REG3[10]_Z2065\: FD port map ( Q => X3_REG3(10), D => X3_REG2(10), C => CLK_C); \X3_REG4[10]_Z2066\: FD port map ( Q => X3_REG4(10), D => X3_REG3(10), C => CLK_C); \X3_REG5[10]_Z2067\: FD port map ( Q => X3_REG5(10), D => X3_REG4(10), C => CLK_C); \X3_REG6[10]\: FD port map ( Q => X3(10), D => X3_REG5(10), C => CLK_C); \X3_REG1[11]_Z2069\: FD port map ( Q => X3_REG1(11), D => X3_1(11), C => CLK_C); \X3_REG2[11]_Z2070\: FD port map ( Q => X3_REG2(11), D => X3_REG1(11), C => CLK_C); \X3_REG3[11]_Z2071\: FD port map ( Q => X3_REG3(11), D => X3_REG2(11), C => CLK_C); \X3_REG4[11]_Z2072\: FD port map ( Q => X3_REG4(11), D => X3_REG3(11), C => CLK_C); \X3_REG5[11]_Z2073\: FD port map ( Q => X3_REG5(11), D => X3_REG4(11), C => CLK_C); \X3_REG6[11]\: FD port map ( Q => X3(11), D => X3_REG5(11), C => CLK_C); \X3_REG1[12]_Z2075\: FD port map ( Q => X3_REG1(12), D => X3_1(12), C => CLK_C); \X3_REG2[12]_Z2076\: FD port map ( Q => X3_REG2(12), D => X3_REG1(12), C => CLK_C); \X3_REG3[12]_Z2077\: FD port map ( Q => X3_REG3(12), D => X3_REG2(12), C => CLK_C); \X3_REG4[12]_Z2078\: FD port map ( Q => X3_REG4(12), D => X3_REG3(12), C => CLK_C); \X3_REG5[12]_Z2079\: FD port map ( Q => X3_REG5(12), D => X3_REG4(12), C => CLK_C); \X3_REG6[12]\: FD port map ( Q => X3(12), D => X3_REG5(12), C => CLK_C); \X3_REG1[13]_Z2081\: FD port map ( Q => X3_REG1(13), D => X3_1(13), C => CLK_C); \X3_REG2[13]_Z2082\: FD port map ( Q => X3_REG2(13), D => X3_REG1(13), C => CLK_C); \X3_REG3[13]_Z2083\: FD port map ( Q => X3_REG3(13), D => X3_REG2(13), C => CLK_C); \X3_REG4[13]_Z2084\: FD port map ( Q => X3_REG4(13), D => X3_REG3(13), C => CLK_C); \X3_REG5[13]_Z2085\: FD port map ( Q => X3_REG5(13), D => X3_REG4(13), C => CLK_C); \X3_REG6[13]\: FD port map ( Q => X3(13), D => X3_REG5(13), C => CLK_C); \X3_REG1[14]_Z2087\: FD port map ( Q => X3_REG1(14), D => X3_1(14), C => CLK_C); \X3_REG2[14]_Z2088\: FD port map ( Q => X3_REG2(14), D => X3_REG1(14), C => CLK_C); \X3_REG3[14]_Z2089\: FD port map ( Q => X3_REG3(14), D => X3_REG2(14), C => CLK_C); \X3_REG4[14]_Z2090\: FD port map ( Q => X3_REG4(14), D => X3_REG3(14), C => CLK_C); \X3_REG5[14]_Z2091\: FD port map ( Q => X3_REG5(14), D => X3_REG4(14), C => CLK_C); \X3_REG6[14]\: FD port map ( Q => X3(14), D => X3_REG5(14), C => CLK_C); \X3_REG1[15]_Z2093\: FD port map ( Q => X3_REG1(15), D => X3_1(15), C => CLK_C); \X3_REG2[15]_Z2094\: FD port map ( Q => X3_REG2(15), D => X3_REG1(15), C => CLK_C); \X3_REG3[15]_Z2095\: FD port map ( Q => X3_REG3(15), D => X3_REG2(15), C => CLK_C); \X3_REG4[15]_Z2096\: FD port map ( Q => X3_REG4(15), D => X3_REG3(15), C => CLK_C); \X3_REG5[15]_Z2097\: FD port map ( Q => X3_REG5(15), D => X3_REG4(15), C => CLK_C); \X3_REG6[15]\: FD port map ( Q => X3(15), D => X3_REG5(15), C => CLK_C); \X3_REG1[16]_Z2099\: FD port map ( Q => X3_REG1(16), D => X3_1(16), C => CLK_C); \X3_REG2[16]_Z2100\: FD port map ( Q => X3_REG2(16), D => X3_REG1(16), C => CLK_C); \X3_REG3[16]_Z2101\: FD port map ( Q => X3_REG3(16), D => X3_REG2(16), C => CLK_C); \X3_REG4[16]_Z2102\: FD port map ( Q => X3_REG4(16), D => X3_REG3(16), C => CLK_C); \X3_REG5[16]_Z2103\: FD port map ( Q => X3_REG5(16), D => X3_REG4(16), C => CLK_C); \X3_REG6[16]\: FD port map ( Q => X3(16), D => X3_REG5(16), C => CLK_C); \X3_REG1[17]_Z2105\: FD port map ( Q => X3_REG1(17), D => X3_1(17), C => CLK_C); \X3_REG2[17]_Z2106\: FD port map ( Q => X3_REG2(17), D => X3_REG1(17), C => CLK_C); \X3_REG3[17]_Z2107\: FD port map ( Q => X3_REG3(17), D => X3_REG2(17), C => CLK_C); \X3_REG4[17]_Z2108\: FD port map ( Q => X3_REG4(17), D => X3_REG3(17), C => CLK_C); \X3_REG5[17]_Z2109\: FD port map ( Q => X3_REG5(17), D => X3_REG4(17), C => CLK_C); \X3_REG6[17]\: FD port map ( Q => X3(17), D => X3_REG5(17), C => CLK_C); \X3_REG1[18]_Z2111\: FD port map ( Q => X3_REG1(18), D => X3_1(18), C => CLK_C); \X3_REG2[18]_Z2112\: FD port map ( Q => X3_REG2(18), D => X3_REG1(18), C => CLK_C); \X3_REG3[18]_Z2113\: FD port map ( Q => X3_REG3(18), D => X3_REG2(18), C => CLK_C); \X3_REG4[18]_Z2114\: FD port map ( Q => X3_REG4(18), D => X3_REG3(18), C => CLK_C); \X3_REG5[18]_Z2115\: FD port map ( Q => X3_REG5(18), D => X3_REG4(18), C => CLK_C); \X3_REG6[18]\: FD port map ( Q => X3(18), D => X3_REG5(18), C => CLK_C); \X3_REG1[19]_Z2117\: FD port map ( Q => X3_REG1(19), D => X3_1(19), C => CLK_C); \X3_REG2[19]_Z2118\: FD port map ( Q => X3_REG2(19), D => X3_REG1(19), C => CLK_C); \X3_REG3[19]_Z2119\: FD port map ( Q => X3_REG3(19), D => X3_REG2(19), C => CLK_C); \X3_REG4[19]_Z2120\: FD port map ( Q => X3_REG4(19), D => X3_REG3(19), C => CLK_C); \X3_REG5[19]_Z2121\: FD port map ( Q => X3_REG5(19), D => X3_REG4(19), C => CLK_C); \X3_REG6[19]\: FD port map ( Q => X3(19), D => X3_REG5(19), C => CLK_C); \X3_REG1[20]_Z2123\: FD port map ( Q => X3_REG1(20), D => X3_1(20), C => CLK_C); \X3_REG2[20]_Z2124\: FD port map ( Q => X3_REG2(20), D => X3_REG1(20), C => CLK_C); \X3_REG3[20]_Z2125\: FD port map ( Q => X3_REG3(20), D => X3_REG2(20), C => CLK_C); \X3_REG4[20]_Z2126\: FD port map ( Q => X3_REG4(20), D => X3_REG3(20), C => CLK_C); \X3_REG5[20]_Z2127\: FD port map ( Q => X3_REG5(20), D => X3_REG4(20), C => CLK_C); \X3_REG6[20]\: FD port map ( Q => X3(20), D => X3_REG5(20), C => CLK_C); \X3_REG1[21]_Z2129\: FD port map ( Q => X3_REG1(21), D => X3_1(21), C => CLK_C); \X3_REG2[21]_Z2130\: FD port map ( Q => X3_REG2(21), D => X3_REG1(21), C => CLK_C); \X3_REG3[21]_Z2131\: FD port map ( Q => X3_REG3(21), D => X3_REG2(21), C => CLK_C); \X3_REG4[21]_Z2132\: FD port map ( Q => X3_REG4(21), D => X3_REG3(21), C => CLK_C); \X3_REG5[21]_Z2133\: FD port map ( Q => X3_REG5(21), D => X3_REG4(21), C => CLK_C); \X3_REG6[21]\: FD port map ( Q => X3(21), D => X3_REG5(21), C => CLK_C); \X3_REG1[22]_Z2135\: FD port map ( Q => X3_REG1(22), D => X3_1(22), C => CLK_C); \X3_REG2[22]_Z2136\: FD port map ( Q => X3_REG2(22), D => X3_REG1(22), C => CLK_C); \X3_REG3[22]_Z2137\: FD port map ( Q => X3_REG3(22), D => X3_REG2(22), C => CLK_C); \X3_REG4[22]_Z2138\: FD port map ( Q => X3_REG4(22), D => X3_REG3(22), C => CLK_C); \X3_REG5[22]_Z2139\: FD port map ( Q => X3_REG5(22), D => X3_REG4(22), C => CLK_C); \X3_REG6[22]\: FD port map ( Q => X3(22), D => X3_REG5(22), C => CLK_C); \X3_REG1[23]_Z2141\: FD port map ( Q => X3_REG1(23), D => X3_1(23), C => CLK_C); \X3_REG2[23]_Z2142\: FD port map ( Q => X3_REG2(23), D => X3_REG1(23), C => CLK_C); \X3_REG3[23]_Z2143\: FD port map ( Q => X3_REG3(23), D => X3_REG2(23), C => CLK_C); \X3_REG4[23]_Z2144\: FD port map ( Q => X3_REG4(23), D => X3_REG3(23), C => CLK_C); \X3_REG5[23]_Z2145\: FD port map ( Q => X3_REG5(23), D => X3_REG4(23), C => CLK_C); \X3_REG6[23]\: FD port map ( Q => X3(23), D => X3_REG5(23), C => CLK_C); \X3_REG1[24]_Z2147\: FD port map ( Q => X3_REG1(24), D => X3_1(24), C => CLK_C); \X3_REG2[24]_Z2148\: FD port map ( Q => X3_REG2(24), D => X3_REG1(24), C => CLK_C); \X3_REG3[24]_Z2149\: FD port map ( Q => X3_REG3(24), D => X3_REG2(24), C => CLK_C); \X3_REG4[24]_Z2150\: FD port map ( Q => X3_REG4(24), D => X3_REG3(24), C => CLK_C); \X3_REG5[24]_Z2151\: FD port map ( Q => X3_REG5(24), D => X3_REG4(24), C => CLK_C); \X3_REG6[24]\: FD port map ( Q => X3(24), D => X3_REG5(24), C => CLK_C); \X3_REG1[25]_Z2153\: FD port map ( Q => X3_REG1(25), D => X3_1(25), C => CLK_C); \X3_REG2[25]_Z2154\: FD port map ( Q => X3_REG2(25), D => X3_REG1(25), C => CLK_C); \X3_REG3[25]_Z2155\: FD port map ( Q => X3_REG3(25), D => X3_REG2(25), C => CLK_C); \X3_REG4[25]_Z2156\: FD port map ( Q => X3_REG4(25), D => X3_REG3(25), C => CLK_C); \X3_REG5[25]_Z2157\: FD port map ( Q => X3_REG5(25), D => X3_REG4(25), C => CLK_C); \X3_REG6[25]\: FD port map ( Q => X3(25), D => X3_REG5(25), C => CLK_C); \X3_REG1[26]_Z2159\: FD port map ( Q => X3_REG1(26), D => X3_1(26), C => CLK_C); \X3_REG2[26]_Z2160\: FD port map ( Q => X3_REG2(26), D => X3_REG1(26), C => CLK_C); \X3_REG3[26]_Z2161\: FD port map ( Q => X3_REG3(26), D => X3_REG2(26), C => CLK_C); \X3_REG4[26]_Z2162\: FD port map ( Q => X3_REG4(26), D => X3_REG3(26), C => CLK_C); \X3_REG5[26]_Z2163\: FD port map ( Q => X3_REG5(26), D => X3_REG4(26), C => CLK_C); \X3_REG6[26]\: FD port map ( Q => X3(26), D => X3_REG5(26), C => CLK_C); \X3_REG1[27]_Z2165\: FD port map ( Q => X3_REG1(27), D => X3_1(27), C => CLK_C); \X3_REG2[27]_Z2166\: FD port map ( Q => X3_REG2(27), D => X3_REG1(27), C => CLK_C); \X3_REG3[27]_Z2167\: FD port map ( Q => X3_REG3(27), D => X3_REG2(27), C => CLK_C); \X3_REG4[27]_Z2168\: FD port map ( Q => X3_REG4(27), D => X3_REG3(27), C => CLK_C); \X3_REG5[27]_Z2169\: FD port map ( Q => X3_REG5(27), D => X3_REG4(27), C => CLK_C); \X3_REG6[27]\: FD port map ( Q => X3(27), D => X3_REG5(27), C => CLK_C); \X3_REG1[28]_Z2171\: FD port map ( Q => X3_REG1(28), D => X3_1(28), C => CLK_C); \X3_REG2[28]_Z2172\: FD port map ( Q => X3_REG2(28), D => X3_REG1(28), C => CLK_C); \X3_REG3[28]_Z2173\: FD port map ( Q => X3_REG3(28), D => X3_REG2(28), C => CLK_C); \X3_REG4[28]_Z2174\: FD port map ( Q => X3_REG4(28), D => X3_REG3(28), C => CLK_C); \X3_REG5[28]_Z2175\: FD port map ( Q => X3_REG5(28), D => X3_REG4(28), C => CLK_C); \X3_REG6[28]\: FD port map ( Q => X3(28), D => X3_REG5(28), C => CLK_C); \X3_REG1[29]_Z2177\: FD port map ( Q => X3_REG1(29), D => X3_1(29), C => CLK_C); \X3_REG2[29]_Z2178\: FD port map ( Q => X3_REG2(29), D => X3_REG1(29), C => CLK_C); \X3_REG3[29]_Z2179\: FD port map ( Q => X3_REG3(29), D => X3_REG2(29), C => CLK_C); \X3_REG4[29]_Z2180\: FD port map ( Q => X3_REG4(29), D => X3_REG3(29), C => CLK_C); \X3_REG5[29]_Z2181\: FD port map ( Q => X3_REG5(29), D => X3_REG4(29), C => CLK_C); \X3_REG6[29]\: FD port map ( Q => X3(29), D => X3_REG5(29), C => CLK_C); \X3_REG1[30]_Z2183\: FD port map ( Q => X3_REG1(30), D => X3_1(30), C => CLK_C); \X3_REG2[30]_Z2184\: FD port map ( Q => X3_REG2(30), D => X3_REG1(30), C => CLK_C); \X3_REG3[30]_Z2185\: FD port map ( Q => X3_REG3(30), D => X3_REG2(30), C => CLK_C); \X3_REG4[30]_Z2186\: FD port map ( Q => X3_REG4(30), D => X3_REG3(30), C => CLK_C); \X3_REG5[30]_Z2187\: FD port map ( Q => X3_REG5(30), D => X3_REG4(30), C => CLK_C); \X3_REG6[30]\: FD port map ( Q => X3(30), D => X3_REG5(30), C => CLK_C); \X3_REG1[31]_Z2189\: FD port map ( Q => X3_REG1(31), D => X3_1(31), C => CLK_C); \X3_REG2[31]_Z2190\: FD port map ( Q => X3_REG2(31), D => X3_REG1(31), C => CLK_C); \X3_REG3[31]_Z2191\: FD port map ( Q => X3_REG3(31), D => X3_REG2(31), C => CLK_C); \X3_REG4[31]_Z2192\: FD port map ( Q => X3_REG4(31), D => X3_REG3(31), C => CLK_C); \X3_REG5[31]_Z2193\: FD port map ( Q => X3_REG5(31), D => X3_REG4(31), C => CLK_C); \X3_REG6[31]\: FD port map ( Q => X3(31), D => X3_REG5(31), C => CLK_C); II_GND: GND port map ( G => NN_1); II_VCC: VCC port map ( P => NN_2); end beh;